UM10503
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User manual
Rev. 1.3 — 6 July 2012
462 of 1269
NXP Semiconductors
UM10503
Chapter 20: LPC43xx SD/MMC interface
20.7.6.2 Initialization
For the SD/MMC DMA initialization, follow these steps:
1. Write to the Bus Mode Register (BMOD) to set the Host bus access parameters.
2. Write to the Interrupt Enable Register (IDINTEN) to mask unnecessary interrupt
causes.
3. The software driver creates either the Transmit or the Receive descriptor list. Then it
writes to Descriptor List Base Address Register (DBADDR), providing the IDMAC with
the starting address of the list.
4. The SD/MMC DMA engine attempts to acquire descriptors from the descriptor lists.
20.7.6.3 Host bus burst access
The SD/MMC DMA attempts to execute fixed-length burst transfers on the AHB Master
interface if configured using the FB bit of the IDMAC Bus Mode register. The maximum
burst length is indicated and limited by the PBL field. The descriptors are always accessed
in the maximum possible burst-size for the 16-bytes to be read: 16*8/bus-width.
The SD/MMC DMA initiates a data transfer only when sufficient space to accommodate
the configured burst is available in the FIFO or the number of bytes to the end of data,
when less than the configured burst-length. The SD/MMC DMA indicates the start
address and the number of transfers required to the AHB Master Interface. When the AHB
Interface is configured for fixed-length bursts, then it transfers data using the best
combination of INCR4/8/16 and SINGLE transactions. Otherwise, in no fixed-length
bursts, it transfers data using INCR (undefined length) and SINGLE transactions.
20.7.6.4 Host data buffer alignment
The transmit and receive data buffers in host memory must be 32-bit aligned.
20.7.6.5 Buffer size calculations
The driver knows the amount of data to transmit or receive. For transmitting to the card,
the IDMAC transfers the exact number of bytes to the FIFO, indicated by the buffer size
field of DES1.
If a descriptor is not marked as last - LS bit of DES0 - then the corresponding buffers of
the descriptor are full, and the amount of valid data in a buffer is accurately indicated by its
buffer size field. If a descriptor is marked as last, then the buffer cannot be full, as
indicated by the buffer size in DES1. The driver is aware of the number of locations that
are valid in this case.
Table 347. SD/MMC DMA DESC3 descriptor
Bit
Symbol
Description
31:0
BAP2
Buffer Address Pointer 2/ Next Descriptor Address
These bits indicate the physical address of the second buffer when the
dual-buffer structure is used. If the Second Address Chained (DES0[4]) bit is
set, then this address contains the pointer to the physical memory where the
Next Descriptor is present.
If this is not the last descriptor, then the Next Descriptor address pointer must be
bus-width aligned (DES3[1:0] = 0 , internally the LSBs are ignored).
