UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
26 of 1269
NXP Semiconductors
UM10503
Chapter 3: LPC43xx Memory mapping
3.6 AHB Multilayer matrix configuration
The multilayer AHB matrix enables all bus masters to access any embedded memory as
well as external SPI flash memory connected to the SPIFI interface. When two or more
bus masters try to access the same slave, a round robin arbitration scheme is used; each
master takes turns accessing the slave in circular order. The access length is determined
by the burst access length of the master. For the CPU, the burst size is 1, for GPDMA, the
burst size can be up to 8. To optimize CPU performance, low-latency code should be
stored in a memory that is not accessed by other bus masters, especially masters that use
a long burst size.
To optimize the CPU performance, the ARM Cortex-M4 has three buses for Instruction
(code) (I) access, Data (D) access, and System (S) access. The I- and D-bus access
memory space is located below 0x2000 0000, the S-bus accesses the memory space
staring from 0x2000 0000. When instructions and data are kept in separate memories,
then code and data accesses can be done in parallel in one cycle. When code and data
are kept in the same memory, then instructions that load or store data may take two
cycles.
The LPC43xx peripherals are divided into AHB and APB peripherals. AHB peripherals
such as the USB and ethernet controllers are directly connected to the AHB matrix. APB
peripherals are connected to the AHB matrix via bus bridges.
