UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
94 of 1269
11.1 How to read this chapter
Ethernet, USB0, USB1, and LCD related clocks are not available on all packages. See
. The corresponding clock control registers are reserved.
The VADC peripheral is available on <tbd> parts only.
11.2 Basic configuration
The CGU is configured as follows:
•
See
for clocking and power control.
•
Do not reset the CGU during normal operation.
•
For using core clock frequencies (BASE_M4_CLK) higher than 110 MHz with the
crystal oscillator, you must change the CGU configuration from the default setting in
several steps. See
11.2.1 Configuring the BASE_M4_CLK for high operating frequencies
To ramp up the clock frequency from low frequencies (< 90 MHz), you must increase the
core clock BASE_M4_CLK in two steps from low frequencies to mid-range frequencies
(90 MHz to 110 MHz) and subsequently from mid-level frequencies to high frequencies
(up to 204 MHz).
The recommended procedure to configure BASE_M4_CLK depends on the current clock
configuration of the part. There are two typical configurations:
1. After a power-up, reset, or when waking up from deep-power down mode. In these
situations, the boot code executes. After the boot process has completed, the clock
configuration of the part is as follows:
–
The core clock BASE_M4_CLK is connected to the output of PLL1 and running at
96 MHz.
–
The clock source for the PLL1 is the 12 MHz IRC.
2. After wake-up from Deep-sleep or power-down modes. In this case, BASE_M4_CLK
is connected to the IRC running at 12 MHz.
No special requirements exist for ramping down BASE_M4_CLK or changing any of the
peripheral base clocks either from low to high or from high to low frequencies.
UM10503
Chapter 11: LPC43xx Clock Generation Unit (CGU)
Rev. 1.3 — 6 July 2012
User manual
Table 62.
CGU clocking and power control
Base clock
Branch clock
Operating frequency
CGU
BASE_M4_CLK
CLK_M4_BUS
up to 204 MHz
