UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
468 of 1269
NXP Semiconductors
UM10503
Chapter 21: LPC43xx External Memory Controller (EMC)
•
Read and write buffers to reduce latency and to improve performance.
•
Separate reset domains allow the for auto-refresh through a chip reset if desired.
•
Programmable delay elements allow to fine-tune the EMC timing.
Remark:
Synchronous static memory devices (synchronous burst mode) are not
supported.
21.4 General description
The LPC43xx External Memory Controller (EMC) is an ARM PrimeCell MultiPort Memory
Controller peripheral offering support for asynchronous static memory devices such as
RAM, ROM and Flash, as well as dynamic memories such as Single Data Rate SDRAM.
Program the EMC_CLKn delays in the EMCDELAYCLK register in the SYSCON block (
), to adjust the delays for
different SDRAM frequencies and operating conditions.
Fig 48. EMC block diagram (SDRAM)
EMC_A[23:0]
EMC_WE
EMC_DYCS[3:0]
EMC_CAS
EMC_RAS
EMC_DQMOUT[3:0]
EMC_D[31:0] (write)
MEMORY
CONTROLLER
STATE
MACHINE
AHB SLAVE
REGISTER
INTERFACE
AHB SLAVE
MEMORY
INTERFACE
EMC
AH
B
MA
TRIX
CLK_M4_EMC/
CLK_M4_EMC_DIV
EMC_CKEOUT[3:0]
EMC_D[31:0] (read)
EMC_CLK[3:0]
programmable
delay
EMCDELAYCLK
DATAIN
FIFO
CLKOUT
SDRAM interface
