UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
349 of 1269
NXP Semiconductors
UM10503
Chapter 18: LPC43xx Serial GPIO (SGPIO)
18.4 General description
Serial GPIO (SGPIO) offer standard GPIO functionality enhanced with features to
accelerate serial stream processing. A data stream on a single SGPIO input or output or
on a dual, quad, and byte lane data input/output is processed by using so called slices. Up
to 16 slices are supported, and all 16 slices have the same basic feature set with some
slices offering additional features.
•
Slices:
–
Each slice supports a 32-bit FIFO, shifted in from a pin or out to a pin at every shift
clock.
–
Some slices control the pin output enable.
–
Slices are double buffered; slices are swapped with the shadow register when the
POS counter reaches 0x0.
–
Slices can be concatenated to increase the buffer size. Software should ensure
that if slice n is concatenated with slice m, POS[n] and POS[m] are equal and run
in phase.
–
Interrupt is raised when the POS counter reaches 0x0.
–
Support for parallel to multi-stream serial conversion and vice versa. Conversion
supports interleaving; Up to 8 bits can be shifted at a time (n= 1, 2, 4 or 8 for serial,
dual-serial, quad-serial and byte parallel IO).
•
Clock:
–
12-bit counter running at SGPIO_CLOCK creates a shift clock to capture input or
create output values. Note that the input frequency should be less than half of the
SGPIO_CLOCK frequency.
–
External input can be used as shift clock. Active edge can be rising or falling (not
both).
–
External input can be used as shift clock qualifier. Can be active LOW or HIGH.
–
Internal signals can be used as shift clock qualifier.
–
POS counter running at shift clock to enable double buffering.
•
Input:
–
Inputs are captured using the shift clock.
–
Inputs can raise interrupt on input level (LOW or HIGH) or transitions (rising, falling
rising or falling). Interrupts can be masked.
–
Interrupts can be raised on a matching pattern. A pattern can be up to 32 bit long
and can be masked (match value = don’t care). Four slices (A, I, H and P) support
mask functionality.
–
Four inputs can be used as shift clock for other slices to capture other inputs.
•
Outputs:
–
Create output: active level (LOW or HIGH) or tri-state. Note if a slice is used to
create an output clock at rate f
out
the slice clock should at least be 2x f
out
. This
limits the data rate per slice to half the SGPIO_CLOCK rate.
–
Output enable can be controlled by other slices. For multi-lane output, the LSB
lane output enable can be controlled independently from the MSB lines.
–
Create output clock from shift clock counter.
