UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
818 of 1269
NXP Semiconductors
UM10503
Chapter 28: LPC43xx State Configurable Timer (SCT)
28.6.2 SCT control register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
CTRL_L (address 0x4000 4004) and CTRL_H (address 0x4000 4006). Both the L and H
registers can be read or written individually or in a single 32-bit read or write operation.
All bits in this register can be written to when the counter is stopped or halted. When the
counter is running, the only bits that can be written are STOP or HALT.(Other bits can be
written in a subsequent write after HALT is set to 1.)
6:3
CLKSEL
SCT clock select
0000
0x0
Rising edges on input 0.
0x1
Falling edges on input 0.
0x2
Rising edges on input 1.
0x3
Falling edges on input 1.
0x4
Rising edges on input 2.
0x5
Falling edges on input 2.
0x6
Rising edges on input 3.
0x7
Falling edges on input 3.
0x8
Rising edges on input 4.
0x9
Falling edges on input 4.
0xA
Rising edges on input 5.
0xB
Falling edges on input 5.
0xC
Rising edges on input 6.
0xD
Falling edges on input 6.
0xE
Rising edges on input 7.
0xF
Falling edges on input 7.
7
NORELAODL_
NORELOADU
-
A 1 in this bit prevents the lower match registers from being reloaded from their
respective reload registers. Software can write to set or clear this bit at any
time. This bit applies to both the higher and lower registers when the UNIFY bit
is set.
0
8
NORELOADH
-
A 1 in this bit prevents the higher match registers from being reloaded from their
respective reload registers. Software can write to set or clear this bit at any
time. This bit is not used when the UNIFY bit is set.
0
16:9
INSYNCn
-
Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A
1 in one of these bits subjects the corresponding input to synchronization to the
SCT clock, before it is used to create an event. If an input is synchronous to the
SCT clock, keep its bit 0 for faster response.
When the CKMODE field is 1x, the bit in this field, corresponding to the input
selected by the CKSEL field, is not used.
1
31:17
-
Reserved
-
Table 647. SCT configuration register (CONFIG - address 0x4000 0000) bit description
…continued
Bit
Symbol
Value
Description
Reset
value
