UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
90 of 1269
NXP Semiconductors
UM10503
Chapter 10: LPC43xx Power Management Controller (PMC)
10.2.3 Deep-sleep mode
In Deep-sleep mode the CPU clock and peripheral clocks are shut down to save power;
logic states and SRAM memory are maintained. All analog blocks and the BOD control
circuit are powered down. The Deep-sleep mode is entered by a WFI or WFE instruction if
the SLEEPDEEP bit in the ARM Cortex-M4 system control register is set to 1 and the
PD0_SLEEP0_MODE register (see
) is programmed with the Deep-sleep mode
value.
When the LPC43xx wakes up from Deep-sleep mode, the 12 MHz IRC is used as the
clock source for all base clocks.
Remark:
Before entering Deep-sleep mode, program the CGU as follows:
•
Switch the clock source of all base clocks to the IRC.
•
Put the PLLs in power-down mode.
Reprogramming the CGU avoids any undefined or unlocked PLL clocks at wake-up and
minimizes power consumption during Deep-sleep mode.
10.2.4 Power-down mode
In Power-down mode the CPU clock and peripheral clocks are shut down but logic states
are maintained. All SRAM memory except for the upper 8 kB of the local SRAM located at
0x1008 0000, all analog blocks, and the BOD control circuit are powered down.The
Power-down mode is entered by a WFI or WFE instruction if the SLEEPDEEP bit in the
ARM Cortex-M4 system control register is set to 1 and the PD0_SLEEP0_MODE register
(see
) is programmed with the Power-down mode value.
When the LPC43xx wakes up from Power-down mode, the 12 MHz IRC is used as the
clock source for all base clocks.
Remark:
Before entering Power-down mode, program the CGU as follows:
•
Switch the clock source of all base clocks to the IRC.
•
Put the PLLs in power-down mode.
Reprogramming the CGU avoids any undefined or unlocked PLL clocks at wake-up and
minimizes power consumption during Power-down mode.
10.2.5 Deep power-down
In Deep power-down mode the entire core logic is powered down and the logic state of the
entire system including the I/O pads is lost. Only the logic in the RTC power domain
remains active. The Deep power-down mode is entered by a WFI or WFE instruction if the
SLEEPDEEP bit in the ARM Cortex-M4 system control register is set to 1 and the
PD0_SLEEP0_MODE register (see
) is programmed with the Deep power-down
value.
When the LPC43xx wakes up from Deep power-down mode, the boot loader configures
the PLL1 as the clock source running at 96 MHz and attempts to boot similar as after a
reset or power-up.
