UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
563 of 1269
NXP Semiconductors
UM10503
Chapter 23: LPC43xx USB0 Host/Device/OTG controller
The states powered, attach, default FS/HS, suspend FS/HS are implemented in the
device controller and are communicated to the DCD using the following status bits:
•
DCSuspend - see
.
•
USB reset received - see
•
Port change detect - see
.
•
High-speed port - see
.
It is the responsibility of the DCD to maintain a state variable to differentiate between the
DefaultFS/HS state and the Address/Configured states. Change of state from Default to
Address and the configured states is part of the enumeration process described in the
Device Framework section of the USB 2.0 Specification
.
As a result of entering the Address state, the device address register (DEVICEADDR)
must be programmed by the DCD.
Entry into the Configured state indicates that all endpoints to be used in the operation of
the device have been properly initialized by programming the ENDPTCTRLx registers and
initializing the associated queue heads.
23.10.3 Bus reset
A bus reset is used by the host to initialize downstream devices. When a bus reset is
detected, the device controller will renegotiate its attachment speed, reset the device
address to 0, and notify the DCD by interrupt (assuming the USB Reset Interrupt Enable
is set). After a reset is received, all endpoints (except endpoint 0) are disabled and any
primed transactions will be cancelled by the device controller. The concept of priming will
be clarified below, but the DCD must perform the following tasks when a reset is received:
•
Clear all setup token semaphores by reading the ENDPTSETUPSTAT register and
writing the same value back to the ENDPTSETUPSTAT register.
•
Clear all the endpoint complete status bits by reading the ENDPTCOMPLETE register
and writing the same value back to the ENDPTCOMPLETE register.
•
Cancel all primed status by waiting until all bits in the ENDPTPRIME register are 0
and then writing 0xFFFFFFFF to the ENDPTFLUSH register.
•
Read the reset bit in the PORTSC1 register and make sure that it is still active. A USB
reset will occur for a minimum of 3 ms and the DCD must reach this point in the reset
cleanup before end of the reset occurs, otherwise a hardware reset of the device
controller is recommended (rare).
Remark:
A hardware reset can be performed by writing a one to the device controller
reset bit in the USBCMD register. A hardware reset will cause the device to detach
from the bus by clearing the Run/Stop bit. Thus, the DCD must completely re-initialize
the device controller after a hardware reset.
•
Free all allocated dTDs because they will no longer be executed by the device
controller. If this is the first time the DCD is processing a USB reset event, then it is
likely that no dTDs have been allocated. At this time, the DCD may release control
back to the OS because no further changes to the device controller are permitted until
a Port Change Detect is indicated.
