NXP Semiconductors LCP43 Series, User Manual

Page: 1155 / 1269

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 1.3 — 6 July 2012 1155 of 1269
NXP Semiconductors
UM10503
Chapter 44: LPC43xx 10-bit ADC0/1
44.2 Basic configuration
The ADC0 and ADC1 are configured as follows:
•
See Table 1006 for clocking and power control.
•
The ADC0 is reset by the ADC0_RST (reset # 40).
•
The ADC1 is reset by the ADC1_RST (reset # 41).
•
The ADC0 interrupt is connected to interrupt slot # 17 in the NVIC.
•
The ADC1 interrupt is connected to interrupt slot # 21 in the NVIC.
•
For connecting to the GPDMA, use the DMAMUX register ( Table 46 ) in the CREG
block and enable the GPDMA channel in the DMA Channel Configuration registers
Section 19.6.20 .
•
External pins (ADCTRIG0/1)and the MOTOCON PWM MCOA2 output can be
selected as conversion triggers for ADC0/1 (see
Table 1010 ).
•
The ADC conversion triggers are connected through the GIMA (see Table 148 ) to the
timers or SCT outputs.
•
For the ADC0 and ADC1 inputs that are multiplexed with digital functions, the pins
need to be configured using the ENAIO0/1 registers (see
Section 15.4.6 and
Section 15.4.8 .
•
The ADC1 channel 7 is connected to the bandgap reference (see Section 15.4.8.1 ).
44.3 Features
•
10 bit successive approximation analog to digital converter.
•
Input multiplexing among 8 pins.
•
Power-down mode.
•
Measurement range 0 to 3.3 V.
•
10-bit conversion time = 2.45

s.
•
Burst conversion mode for single or multiple inputs.
•
Optional conversion on transition on input pin or Timer Match signal.
•
Individual result registers for each A/D channel to reduce interrupt overhead.\
•
Connected to bandgap reference (see Section 15.4.8.1 ).
Table 1006.ADC0/1 clocking and power control
Base clock Branch clock Operating
frequency Notes
ADC0 clock BASE_APB3_CLK CLK_APB3_ADC0 up to 204 MHz For register interface and
ADC0 conversion rate.
ADC1 clock BASE_APB3_CLK CLK_APB3_ADC1 up to 204 MHz For register interface and
ADC1 conversion rate.