M451
May. 4, 2018
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Rev.2.08
M4
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Edge Detect
Brake Interrupt
BRKEIF0 or BRKEIF1 (PWM_INTSTS1[1:0])
BRK_INT
Low level
detection
Level Detect
Brake Interrupt
BRKEIEN0_1 (PWM_INTEN1[0])
BRKLIF0 or BRKLIF1
(PWM_INTSTS1[9:8])
BRKLIEN0_1 (PWM_INTEN1[8])
Edge Detect
Brake Source
Level Detect
Brake Source
Note:
denotes falling edge detect
BRKESTS0
(PWM_INTSTS1[16])
PWM_OUT1
PWM_OUT0
BRKLSTS0 (PWM_INTSTS1[24])
BRKESTS1(PWM_INTSTS1[17])
BRKLSTS1(PWM_INTSTS1[25])
BRKAEVEN
(PWM_BRKCTL0[17:16])
BRKAODD
(PWM_BRKCTL0[19:18])
Figure 6.9-30 Brake Block Diagram for PWM_CH0 and PWM_CH1 Pair
Figure 6.9-31 illustrates the edge detector waveform for PWM_CH0 and PWM_CH1 pair. In this
case, the edge detect brake source has occurred twice for the brake events. When the event
occurs, both of the BRKEIF0 and BRKEIF1 flags are set and BRKESTS0 and BRKESTS1 are
also set to indicate brake state of PWM_CH0 and PWM_CH1. For the first occurring event,
software writes 1 to clear the BRKEIF0. After that, the BRKESTS0 is cleared by hardware at the
next start of the PWM period. At the same moment, the PWM_CH0 outputs the normal waveform
even though the brake event is still occurring. The second event also triggers the same flags, but
at this time, software writes 1 to clear the BRKEIF1. Afterward, PWM_CH1 outputs normally at
the next start of the PWM period.
As a contrast to the edge detector example, Figure 6.9-32 illustrates the level detector waveform
for PWM_CH0 and PWM_CH1 pair. In this case, the BRKLIF0 and BRKLIF1 can only indicate the
brake event having occurred. The BRKLSTS0 and BRKLSTS1 brake states will automatically
recover at the start of the next PWM period no matter at what states the BRKLIF0 and BRKLIF1
are at that moment.
