M451
May. 4, 2018
Page
690
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1006
Rev.2.08
M4
51
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Data Transfer
When a slave receives a correct address with an R/W bit, the data will follow R/W bit specified to
transfer. Each transferred byte is followed by an acknowledge bit on the 9th SCL clock cycle. If
the slave signals a Not Acknowledge (NACK), the master can generate a STOP signal to abort
the data transfer or generate a Repeated START signal and start a new transfer cycle.
If the master, as a receiving device, does Not Acknowledge (NACK) the slave, the slave releases
the SDA line for the master to generate a STOP or Repeated START signal.
SDA
SCL
Data line stable;
data valid
Change of data
allowed
Figure 6.15-5 Bit Transfer on the I
2
C Bus
Data output by
transmitter
SCL from
master
START
condition
acknowlegde
Data output
by receiver
S
1
2
8
9
Clock pulse for
acknowledgement
not acknowlegde
Figure 6.15-6 Acknowledge on the I
2
C Bus
