M451
May. 4, 2018
Page
394
of
1006
Rev.2.08
M4
51
S
E
RI
E
S
T
E
CH
NICA
L RE
F
E
R
E
NC
E
M
A
NU
A
L
PDMA Transfer Stop Control Register (PDMA_STOP)
Register
Offset
R/W Description
Reset Value
PDMA_STOP
P 0x404
W
PDMA Transfer Stop Control Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
STOP11
STOP10
STOP9
STOP8
7
6
5
4
3
2
1
0
STOP7
STOP6
STOP5
STOP4
STOP3
STOP2
STOP1
STOP0
Bits
Description
[31:12]
Reserved
Reserved.
[11:0]
STOPn
PDMA Transfer Stop Control Register (Write Only)
User can stop the PDMA transfer by STOPn bit field or by software reset (writing
‘0xFFFF_FFFF’ to PDMA_STOP register).
By bit field:
0 = No effect.
1 = Stop PDMA transfer[n]. When software set PDMA_STOP bit, the operation will finish
the on-going transfer channel and then clear the channel enable bit (PDMA_CHCTL
[CHEN]) and request active flag.
By write 0xFFFF_FFFF to PDMA_STOP:
Setting all PDMA_STOP bit to “1” will generate software reset to reset internal state
machine (the DSCT will not be reset). When software reset, the operation will be stopped
imminently that include the on-going transfer and the channel enable bit (PDMA_CHCTL
[CHEN]) and request active flag will be cleared to ‘0’.
Note1:
User can read channel enable bit to know if the on-going transfer is finished.
Note2:
STOP8~11 is M45xG/M45xE only.
Note:
The n in the descriptor table represents the PDMA channel.
