M451
May. 4, 2018
Page
272
of
1006
Rev.2.08
M4
51
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6.3.5 Power-down Mode Clock
When entering Power-down mode, system clocks, some clock sources and some peripheral
clocks are disabled. Some clock sources and peripherals clock are still active in Power-down
mode.
For theses clocks, which still keep active, are listed below:
Clock Generator
10 kHz internal low speed RC oscillator (LIRC) clock
32.768 kHz external low speed crystal oscillator (LXT) clock
Peripherals Clock (When the modules adopt LXT or LIRC as clock source)
6.3.6 Clock Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided
clocks with the frequency from F
in
/2
1
to F
in
/2
16
where F
in
is input clock frequency to the clock
divider.
The output formula is
F
out
= F
in
/2
(N+1)
,
where F
in
is the input clock frequency, F
out
is the clock
divider output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When
writing 0 to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock
reaches low state and stays in low state.
11
10
01
00
HCLK
LXT
HXT
HIRC
CLKOSEL (CLK_CLKSEL1[29:28])
CLKOCKEN (CLK_APBCLK0[6])
CLKO_CLK
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-6 Clock Source of Clock Output
