M451
May. 4, 2018
Page
276
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1006
Rev.2.08
M4
51
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source selection. The clocks of peripheral are not controlled by Power-down mode, if the
peripheral clock source is from LXT or LIRC.
0 = Chip operating normally or chip in idle mode because of WFI command.
1 = Chip enters Power-down mode instant or wait CPU sleep command WFI.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[6]
PDWKIF
Power-down Mode Wake-up Interrupt Status
Set by “Power-down wake-up event”, it indicates that resume from Power-down mode”
The flag is set if the EINT0~5, GPIO, USBH, USBD, OTG, UART0~3, WDT, CAN0,
ACMP01, BOD, RTC, TMR0~3, I
2
C0~1.
Note1:
Write 1 to clear the bit to 0.
Note2:
This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
[5]
PDWKIEN
Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)
0 = Power-down mode wake-up interrupt Disabled.
1 = Power-down mode wake-up interrupt Enabled.
Note1:
The interrupt will occur when both PDWKIF and PDWKIEN are high.
Note2:
This bit is write protected. Refer to the SYS_REGLCTL register.
[4]
PDWKDLY
Enable the Wake-up Delay Counter (Write Protect)
When the chip wakes up from Power-down mode, the clock control will delay certain clock
cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip works at 4~20 MHz external high
speed crystal oscillator (HXT), and 256 clock cycles when chip works at 22.1184 MHz
internal high speed RC oscillator (HIRC).
0 = Clock cycles delay Disabled.
1 = Clock cycles delay Enabled.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[3]
LIRCEN
LIRC Enable Bit (Write Protect)
0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled.
1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[2]
HIRCEN
HIRC Enable Bit (Write Protect)
0 = 22.1184 MHz internal high speed RC oscillator (HIRC) Disabled.
1 = 22.1184 MHz internal high speed RC oscillator (HIRC) Enabled.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[1]
LXTEN
LXT Enable Bit (Write Protect)
0 = 32.768 kHz external low speed crystal (LXT) Disabled.
1 = 32.768 kHz external low speed crystal (LXT) Enabled.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[0]
HXTEN
HXT Enable Bit (Write Protect)
The bit default value is set by flash controller user configuration register CONFIG0 [26:24].
When the default clock source is from HXT, this bit is set to 1 automatically.
0 = 4~20 MHz xxternal high speed crystal (HXT) Disabled.
1 = 4~20 MHz external high speed crystal (HXT) Enabled.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
Register/Instruction
Mode
SLEEPDEEP
(SCR[2])
PDEN
(CLK_PWRCTL
PDWTCPU
(CLK_PWRCTL
CPU Run WFI
Instruction
Clock Disable
