M451
May. 4, 2018
Page
559
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1006
Rev.2.08
M4
51
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check rationality between RTC_WEEKDAY and RTC_CAL either.
RTC Read/Write Enable
6.12.5.3
The RWEN bits (RTC_RWEN[15:0]) is served as read/write access of RTC registers to unlock
register read/write protection function. If RTC_RWEN[15:0] is written to 0xa965, user can read
register access enable flag RWENF (RTC_RWEN[16]) to check the RTC registers are read/write
accessible or locked. Once RWENF bit is enabled, RTC access enable function will keep effect at
least 1024 RTC clocks (about 30ms) and RWENF bit will be cleared automatically after 1024 RTC
clocks. The RTC control registers access attribute when RWENF is 1 and 0 are shown in the
Table 6-20.
Register
RWENF=1
RWENF=0
RTC_INIT
R/W
R/W
RTC_RWEN
R/W
R/W
RTC_FREQADJ
R/W
Not available
RTC_TIME
R/W
R
RTC_CAL
R/W
R
RTC_CLKFMT
R/W
R/W
RTC_WEEKDAY
R/W
R
RTC_TALM
R/W
Not available
RTC_CALM
R/W
Not available
MRTC_TALM
R/W
R
RTC_CAMSK
R/W
R
RTC_LEAPYEAR
R
R
RTC_INTEN
R/W
R/W
RTC_INTSTS
R/W
R/W
RTC_TICK
R/W
Not available
RTC_SPRCTL
R/W
Not available
RTC_SPR0-RTC_SPR19
R/W
Not available
RTC_LXTCTL
R/W
Not available
RTC_LXTOCTL
R/W
Not available
RTC_LXTICTL
R/W
Not available
RTC_TAMPCTL
R/W
Not available
Table 6-20 RTC control registers access attribute
Frequency Compensation
6.12.5.4
The RTC source clock may not precise to exactly 32768 Hz and the RTC_FREQADJ register
allows user to make digital compensation to the RTC source clock only if the frequency of RTC
source clock is in the range from 32761 Hz to 32776 Hz.
Integer Part Of Detected Value
INTEGER
(RTC_FREQADJ[11:8])
Integer Part Of Detected Value
INTEGER
(RTC_FREQADJ[11:8])
