M451
May. 4, 2018
Page
985
of
1006
Rev.2.08
M4
51
S
E
RI
E
S
T
E
CH
NICA
L RE
F
E
R
E
NC
E
M
A
NU
A
L
DAC Timing Control Register (DAC_TCTL)
Register
Offset
R/W
Description
Reset Value
DAC_TCTL
0x14
R/W
DAC Timing Control Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
SETTLET
7
6
5
4
3
2
1
0
SETTLET
Bits
Description
[31:10]
Reserved
Reserved.
[9:0]
SETTLET
DAC Output Settling Time
User software needs to write appropriate value to these bits to meet DAC conversion
settling time base on PCLK (APB clock) speed.
For example, DAC controller clock speed is 72MHz and DAC conversion setting time is 1
us, SETTLET value must be greater than 0x48.
