M451
May. 4, 2018
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Rev.2.08
M4
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Error Code
Meanings
0
No Error
1
Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message
where this is not allowed.
2
Form Error: A fixed format part of a received frame has the wrong format.
3
AckError: The message this CAN Core transmitted was not acknowledged by another node.
4
Bit1Error: During the transmission of a message (with the exception of the arbitration field), the
device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus value was
dominant.
5
Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or
overload flag), though the device wanted to send a dominant level (data or identifier bit logical
value ‘0’), but the monitored Bus value was recessive. During bus-off recovery, this status is set
each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor
the proceedings of the bus-off recovery sequence (indicating the bus is not stuck at dominant or
continuously disturbed).
6
CRCError: The CRC check sum was incorrect in the message received, the CRC received for an
incoming message does not match with the calculated CRC for the received data.
7
Unused: When the LEC shows the value ‘7’, no CAN bus event was detected since the CPU wrote
this value to the LEC.
Table 6-40 Last Error Code
Status Interrupts
A Status Interrupt is generated by bits BOff (CAN_STATUS[7]) and EWarn (CAN_STATUS[6]) (Error
Interrupt) or by RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]) and LEC (CAN_STATUS[2:0])
(Status Change Interrupt) assumed that the corresponding enable bits in the CAN Control Register are
set. A change of bit EPass (CAN_STATUS[5]) or a write to RxOk, TxOk or LEC will never generate a
Status Interrupt.
Reading the Status Register will clear the Status Interrupt value (8000h) in the Interrupt Register, if it
is pending.
