M451
May. 4, 2018
Page
277
of
1006
Rev.2.08
M4
51
S
E
RI
E
S
T
E
CH
NICA
L RE
F
E
R
E
NC
E
M
A
NU
A
L
[7])
[8])
Normal operation
0
0
0
NO
All clocks are controlled by
control register.
Idle mode
(CPU enter Sleep
mode)
0
0
0
YES
Only CPU clock is disabled.
Power-down mode
(CPU enters Deep
Sleep mode)
1
1
1
YES
Most clocks are disabled
except LIRC/LXT, and only
RTC/WDT/Timer peripheral
clocks still enable if their
clock sources are selected
as LIRC/LXT.
Table 6-9 Power-down Mode Control Table
When the chip enters Power-down mode, user can wake up chip by some interrupt sources. User
should enable the related interrupt sources and NVIC IRQ enable bits (NVIC_ISER) before set PDEN
bit in CLK_PWRCTL[7] to ensure chip can enter Power-down and wake up successfully.
