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M451
May. 4, 2018
Page
525
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1006
Rev.2.08
M4
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PWM Status Register (PWM_STATUS)
Register
Offset
R/W
Description
Reset Value
PWM_STATU
S
0x120 R/W
PWM Status Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
DACTRGF
23
22
21
20
19
18
17
16
Reserved
ADCTRGF5
ADCTRGF4
ADCTRGF3
ADCTRGF2
ADCTRGF1
ADCTRGF0
15
14
13
12
11
10
9
8
Reserved
SYNCINF4
SYNCINF2
SYNCINF0
7
6
5
4
3
2
1
0
Reserved
CNTMAXF5
CNTMAXF4
CNTMAXF3
CNTMAXF2
CNTMAXF1
CNTMAXF0
Bits
Description
[31:25]
Reserved
Reserved.
[24]
DACTRGF
DAC Start of Conversion Flag
0 = Indicates no DAC start of conversion trigger event has occurred.
1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1
to clear this bit.
[23:22]
Reserved
Reserved.
[21:16]
ADCTRGFn
EADC Start of Conversion Flag
Each bit n controls the corresponding PWM channel n.
0 = Indicates no EADC start of conversion trigger event has occurred.
1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1
to clear this bit.
[15:11]
Reserved
Reserved.
[10:8]
SYNCINFn
Input Synchronization Latched Flag
Each bit n controls the corresponding PWM channel n.
0 = Indicates no SYNC_IN event has occurred.
1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
[7:6]
Reserved
Reserved.
[5:0]
CNTMAXFn
Time-base Counter Equal to 0xFFFF Latched Flag
Each bit n controls the corresponding PWM channel n.
0 = indicates the time-base counter never reached its maximum value 0xFFFF.
1 = indicates the time-base counter reached its maximum value, software can write 1 to
clear this bit.