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M451
May. 4, 2018
Page
398
of
1006
Rev.2.08
M4
51
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NICA
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NC
E
M
A
NU
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PDMA Fix Priority Clear Register (PDMA_PRICLR)
Register
Offset
R/W Description
Reset Value
PDMA_PRICLR
P 0x414
W
PDMA Fixed Priority Clear Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
FPRICLR11
FPRICLR10
FPRICLR9
FPRICLR8
7
6
5
4
3
2
1
0
FPRICLR7
FPRICLR6
FPRICLR5
FPRICLR4
FPRICLR3
FPRICLR2
FPRICLR1
FPRICLR0
Bits
Description
[31:12]
Reserved
Reserved.
[11:0]
FPRICLRn
PDMA Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
0 = No effect.
1 = Clear PDMA channel [n] fixed priority setting.
Note1:
User can read PDMA_PRISET register to know the channel priority.
Note2:
FPRICLR8~11 is M45xG/M45xE only.
Note:
The n in the descriptor table represents the PDMA channel.