M451
May. 4, 2018
Page
707
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1006
Rev.2.08
M4
51
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Data Register (I2C_DAT)
This register contains a byte of serial data to be transmitted or a byte which just has been
received. The CPU can be read from or written to the 8-bit (I2C_DAT [7:0]) directly while it is not
in the process of shifting a byte. When I
2
C is in a defined state and the serial interrupt flag (SI) is
set, data in I2C_DAT [7:0] remains stable. While data is being shifted out, data on the bus is
simultaneously being shifted in; I2C_DAT [7:0] always contains the last data byte presented on
the bus.
The acknowledge bit is controlled by the I
2
C hardware and cannot be accessed by the CPU.
Serial data is shifted into I2C_DAT [7:0] on the rising edges of serial clock pulses on the SCL line.
When a byte has been shifted into I2C_DAT [7:0], the serial data is available in I2C_DAT [7:0],
and the acknowledge bit (ACK or NACK) is returned by the control logic during the ninth clock
pulse. In order to monitor bus status while sending data, the bus date will be shifted to
I2C_DAT[7:0] when sending I2C_DAT[7:0] to bus. In the case of sending data, serial data bits are
shifted out from I2C_DAT [7:0] on the falling edge of SCL clocks, and is shifted to I2C_DAT [7:0]
on the rising edge of SCL clocks.
I2DAT.7 I2DAT.6 I2DAT.5 I2DAT.4 I2DAT.3 I2DAT.2 I2DAT.1 I2DAT.0
I
2
C
Data Register:
shifting direction
Figure 6.15-20 I
2
C Data Shifting Direction
