M451
May. 4, 2018
Page
383
of
1006
Rev.2.08
M4
51
S
E
RI
E
S
T
E
CH
NICA
L RE
F
E
R
E
NC
E
M
A
NU
A
L
Transfer Type
6.7.5.3
The PDMA controller supports two transfer types: single transfer type and burst transfer type,
configure by setting TXTYPE (PDMA_DSCTn_CTL[2]).
When PDMA controller operated in single transfer type, each transfer data needs one request
signal for one transfer, after transferred data, TXCNT (PDMA_DSCTn_CTL[29:16]) will decrease
1. Transfer will finish until the TXCNT (PDMA_DSCTn_CTL[29:16]) decrease to 0. In this mode,
the BURSIZE (PDMA_DSCTn_CTL[6:4]) is not useful to control the transfer size. The BURSIZE
(PDMA_DSCTn_CTL[6:4]) will be fixed as one.
For the burst transfer type, PDMA controller transfers TXCNT (PDMA_DSCTn_CTL[29:16]) of
data and need only one request signal. After transferred BURSIZE (PDMA_DSCTn_CTL[6:4]) of
data, TXCNT (PDMA_DSCTn_CTL[29:16]) will decrease BURSIZE number. Transfer will done
until the transfer count TXCNT (PDMA_DSCTn_CTL[29:16]) decrease to 0.
Note that burst transfer type can only be used for PDMA controller to do burst transfer between
memory and memory. User must use single request type for memory-to-peripheral and
peripheral-to-memory transfers.
Figure 6.7-6 shows an example about single and burst transfer type in basic mode. In this
example, channel 1 uses single transfer type and TXCNT (PDMA_DSCTn_CTL[29:16]) = 128.
Channel 0 uses burst transfer type, BURSIZE (PDMA_DSCTn_CTL[6:4]) = 128 and TXCNT
(PDMA_DSCTn_CTL[29:16]) = 256. The operation sequence is described below:
1. Channel 0 and channel 1 get the trigger signal at the same time.
2. Channel 1 has higher priority than channel 0 by default; the PDMA controller will load the
channel 1 descriptor table first and executing. But channel 1 is single transfer type, so PDMA
controller will only transfer one transfer data.
3. T
hen, PDMA controller turns to the channel 0 and loads channel 0’s descriptor table. The
channel 0 is burst transfer type and the burst size selected to 128. Therefore, PDMA
controller will transfer 128 transfer data.
4. When channel 0 transfers 128 data, channel 1 gets another request signal, then after
channel 0 finishes 128 transfer data, the PDMA controller will turn to channel 1 and transfer
next one data.
5. After channel 1 transfers data, PDMA controller switches to low priority channel 0 to
continuous next 128 data transfer. If no channel 1 request receives, PDMA will start next
channel 0, 128 data transfer.
6. PDMA controller will complete transfer when channel 0 finishes data transfer 256 times, and
channel 1 finishes transferring 128 times.
