Nuvoton ARM Cortex NuMicro M451 Series, Technical Reference Manual

Page: 765 / 1006

M451
May. 4, 2018 Page 765 of 1006 Rev.2.08
M4
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6.16.8 Register Map
R : read only, W : write only, R/W : both read and write
Register Offset R/W Description Reset Value
SPI Base Address:
SPIn_BA = 0x400 (0x1000 * n)
n= 0,1,2
SPI_CTL
0x00 R/W SPI Control Register 0x0000_0034
SPI_CLKDIV 0x04 R/W SPI Clock Divider Register 0x0000_0000
SPI_SSCTL
0x08 R/W SPI Slave Select Control Register 0x0000_0000
SPI_PDMACTL 0x0C R/W SPI PDMA Control Register 0x0000_0000
SPI_FIFOCTL 0x10 R/W SPI FIFO Control Register 0x4400_0000
SPI_STATUS 0x14 R/W SPI Status Register 0x0005_0110
SPI_TX 0x20 W Data Transmit Register 0x0000_0000
SPI_RX
0x30 R Data Receive Register 0x0000_0000
SPI_I2SCTL 0x60 R/W I
2
S Control Register 0x0000_0000
SPI_I2SCLK
0x64 R/W I
2
S Clock Divider Control Register 0x0000_0000
SPI_I2SSTS 0x68 R/W I
2
S Status Register 0x0005_0100
Note: SPIn_BA indicates each set of SPI, and there are SPI0_BA, SPI1_BA, and SPI2_BA.