M451
May. 4, 2018
Page
717
of
1006
Rev.2.08
M4
51
S
E
RI
E
S
T
E
CH
NICA
L RE
F
E
R
E
NC
E
M
A
NU
A
L
I
2
C Bus Management Timer and I
2
C CLock Low Timer Register (I2C_BUSTOUT/ I2C_CLKTOUT)
Both of the definition of these registers are described in the time-out section of SM Bus.
Example for Random Read on EEPROM
6.15.5.4
The following steps are used to configure the I
2
C0 related registers when using I
2
C to read data
from EEPROM.
1.
Set I
2
C0 the multi-function pin in the SYS_GPA_MFPL or SYS_GPD_MFPL or
SYS_GPE_MFPH or SYS_GPA_MFPH registers as SCL and SDA pins.
2.
Enable I
2
C0 APB clock, I2C0CK
EN=1 in the “CLK_APBCLK0” register.
3.
Set I2C0RST=1 to reset I
2
C0 controller then set I
2
C0 controller to normal operation,
I2C0
RST=0 in the “SYS_IPRST1” register.
4.
Set I2CEN=1 to enable I
2
C0
controller in the “I2C_CTL” register.
5.
Give I
2
C0 clock a divided register value for I
2
C clock rate in the “I2C_CLKDIV”.
6.
Set SETENA=0x0000004
0 in the “NVIC_ISER2” register to set I
2
C0 IRQ.
7.
Set INTEN=1 to enable I
2
C0
Interrupt in the “I2C_CTL” register.
8.
Set I
2
C0
address registers “I2C_ADDR0 ~ I2C_ADDR3”.
Random read operation is one of the methods of access EEPROM. The method allows the
master to access any address of EEPROM space. The Figure 6.15-22 shows the EEPROM
random read operation.
S
T
A
1 0 1 0
A
2
A
1
A
0
W
A
C
K
X X X
A
C
K
A
C
K
S
T
1 0 1 0
A
2
A
1
A
0
R
A
C
K
N
A
C
K
S
T
O
DATA BYTE
ROM ADDRRSS
LOW BYTE
ROM ADDRRSS
HIGH BYTE
SLA+W
SDA
LINE
SLA+R
Figure 6.15-22 EEPROM Random Read
The Figure 6.15-23 shows how to use I
2
C controller to implement the protocol of EEPROM
random read.
