M451
May. 4, 2018
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Rev.2.08
M4
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Note:
The bus-off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by
setting or resetting the Init bit (CAN_CON[0]). If the device goes in the bus-off state, it will set Init of its
own accord, stopping all bus activities. Once Init has been cleared by the CPU, the device will then
wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal
operations. At the end of the bus-off recovery sequence, the Error Management Counters will be
reset.
During the waiting time after resetting Init, each time a sequence of 11 recessive bits has been
monitored, a Bit0Error code is written to the Status Register, enabling the CPU to readily check up
whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the proceeding of
the bus-off recovery sequence.
