M451
May. 4, 2018
Page
283
of
1006
Rev.2.08
M4
51
S
E
RI
E
S
T
E
CH
NICA
L RE
F
E
R
E
NC
E
M
A
NU
A
L
Clock Source Select Control Register 0 (CLK_CLKSEL0)
Register
Offset
R/W
Description
Reset Value
CLK_CLKSEL
0
0x10
R/W
Clock Source Select Control Register 0
0x0000_003X
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
PCLK1SEL
PCLK0SEL
STCLKSEL
HCLKSEL
Bits
Description
[31:8]
Reserved
Reserved.
[7]
PCLK1SEL
PCLK1 Clock Source Selection (Write Protect)
0 = APB1 bus clock source from HCLK.
1 = APB1 bus clock source from HCLK/2.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[6]
PCLK0SEL
PCLK0 Clock Source Selection (Write Protect)
0 = APB0 bus clock source from HCLK.
1 = APB0 bus clock source from HCLK/2.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[5:3]
STCLKSEL
Cortex
®
-M4 SysTick Clock Source Selection (Write Protect)
If SYST_CTRL[2]=0, SysTick uses listed clock source below.
000 = Clock source from HXT.
001 = Clock source from LXT.
010 = Clock source from HXT/2.
011 = Clock source from HCLK/2.
111 = Clock source from HIRC/2.
Note:
if SysTick clock source is not from HCLK (i.e. SYST_CTRL[2] = 0), SysTick clock
source must less than or equal to HCLK/2.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[2:0]
HCLKSEL
HCLK Clock Source Selection (Write Protect)
Before clock switching, the related clock sources (both pre-select and new-select) must be
turned on.
The default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user
configuration register of Flash controller by any reset. Therefore the default value is either
000b or 111b.
000 = Clock source from HXT.
001 = Clock source from LXT.
010 = Clock source from PLL.
