M451
May. 4, 2018
Page
662
of
1006
Rev.2.08
M4
51
S
E
RI
E
S
T
E
CH
NICA
L RE
F
E
R
E
NC
E
M
A
NU
A
L
SC Alternate Control Register (SC_ALTCTL)
Register
Offset
R/W
Description
Reset Value
SC_ALTCTL
SC_BA+0x08
R/W
SC Alternate Control Register.
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
ACTSTS2
ACTSTS1
ACTSTS0
RXBGTEN
ADACEN
Reserved
INITSEL
7
6
5
4
3
2
1
0
CNTEN2
CNTEN1
CNTEN0
WARSTEN
ACTEN
DACTEN
RXRST
TXRST
Bits
Description
[31:16]
Reserved
Reserved.
[15]
ACTSTS2
Internal Timer2 Active State (Read Only)
This bit indicates the timer counter status of timer2.
0 = Timer2 is not active.
1 = Timer2 is active.
[14]
ACTSTS1
Internal Timer1 Active State (Read Only)
This bit indicates the timer counter status of timer1.
0 = Timer1 is not active.
1 = Timer1 is active.
[13]
ACTSTS0
Internal Timer0 Active State (Read Only)
This bit indicates the timer counter status of timer0.
0 = Timer0 is not active.
1 = Timer0 is active.
[12]
RXBGTEN
Receiver Block Guard Time Function Enable Bit
0 = Receiver block guard time function Disabled.
1 = Receiver block guard time function Enabled.
[11]
ADACEN
Auto Deactivation When Card Removal
0 = Auto deactivation Disabled when hardware detected the card removal.
1 = Auto deactivation Enabled when hardware detected the card removal.
Note:
When the card is removed, hardware will stop any process and then do deactivation
sequence (if this bit is set). If this process completes, hardware will generate an interrupt
INITIF to CPU.
[10]
Reserved
Reserved.
[9:8]
INITSEL
Initial Timing Selection
This fields indicates the timing of hardware initial state (activation or warm-reset or
deactivation).
Unit: SC clock
