M451
May. 4, 2018
Page
246
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1006
Rev.2.08
M4
51
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NICA
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IRQ0 ~ IRQ63 Clear-Pending Control Register (NVIC_ICPR1)
Register
Offset
R/W
Description
Reset Value
NVIC_ICPR1
0x180
R/W
IRQ0 ~ IRQ63 Clear-Pending Control Register
0x0000_0000
31
30
29
28
27
26
25
24
CALPEND
23
22
21
20
19
18
17
16
CALPEND
15
14
13
12
11
10
9
8
CALPEND
7
6
5
4
3
2
1
0
CALPEND
Bits
Description
[31:0]
CALPEND
Interrupt Clear-pending
The NVIC_ICPR0-NVIC_ICPR2 registers remove the pending state from interrupts, and
show which interrupts are pending
Write Operation:
0 = No effect.
1 = Removes pending state an interrupt.
Read Operation:
0 = Interrupt is not pending.
1 = Interrupt is pending.
