Nuvoton ARM Cortex NuMicro M451 Series, Technical Reference Manual

Page: 782 / 1006

M451
May. 4, 2018 Page 782 of 1006 Rev.2.08
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2
S Clock Divider Control Register (SPI_I2SCLK)
Register Offset R/W Description Reset Value
SPI_I2SCLK 0x64 R/W I
2
S Clock Divider Control Register 0x0000_0000
Note: Not supported in SPI mode.
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved BCLKDIV
15 14 13 12 11 10 9 8
BCLKDIV
7 6 5 4 3 2 1 0
Reserved MCLKDIV
Bits Description
[31:17] Reserved Reserved.
[16:8] BCLKDIV
Bit Clock Divider
The I
2
S controller will generate bit clock in Master mode. The bit clock rate, F_I2SBCLK, is
determined by the following expression.
F_I2SBCLK = F_I2SCLK /(2x(B 1)) , where F_I2SCLK is the frequency of I
2
S
source clock determined by SPInSEL setting of CLK_CLKSEL2 register.
[7:6] Reserved Reserved.
[5:0]
MCLKDIV
Master Clock Divider
If MCLKEN is set to 1, I
2
S controller will generate master clock for external audio devices.
The master clock rate, F_I2SMCLK, is determined by the following expressions.
If MCLKDIV >= 1, F_I2SMCLK = F_I2SCLK/(2x(MCLKDIV)).
If MCLKDIV = 0, F_I2SMCLK = F_I2SCLK.
F_I2SCLK is the frequency of I
2
S source clock determined by SPInSEL setting of
CLK_CLKSEL2 register.
In general, the master clock rate is 256 times sampling clock rate.