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M451
May. 4, 2018
Page
527
of
1006
Rev.2.08
M4
51
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NICA
L RE
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E
NC
E
M
A
NU
A
L
PWM Capture Control Register (PWM_CAPCTL)
Register
Offset
R/W
Description
Reset Value
PWM_CAPCT
L
0x204 R/W
PWM Capture Control Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
FCRLDEN5
FCRLDEN4
FCRLDEN3
FCRLDEN2
FCRLDEN1
FCRLDEN0
23
22
21
20
19
18
17
16
Reserved
RCRLDEN5
RCRLDEN4
RCRLDEN3
RCRLDEN2
RCRLDEN1
RCRLDEN0
15
14
13
12
11
10
9
8
Reserved
CAPINV5
CAPINV4
CAPINV3
CAPINV2
CAPINV1
CAPINV0
7
6
5
4
3
2
1
0
Reserved
CAPEN5
CAPEN4
CAPEN3
CAPEN2
CAPEN1
CAPEN0
Bits
Description
[31:30]
Reserved
Reserved.
[29:24]
FCRLDENn
Falling Capture Reload Enable Bits
Each bit n controls the corresponding PWM channel n.
0 = Falling capture reload counter Disabled.
1 = Falling capture reload counter Enabled.
[23:22]
Reserved
Reserved.
[21:16]
RCRLDENn
Rising Capture Reload Enable Bits
Each bit n controls the corresponding PWM channel n.
0 = Rising capture reload counter Disabled.
1 = Rising capture reload counter Enabled.
[15:14]
Reserved
Reserved.
[13:8]
CAPINVn
Capture Inverter Enable Bits
Each bit n controls the corresponding PWM channel n.
0 = Capture source inverter Disabled.
1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
[7:6]
Reserved
Reserved.
[5:0]
CAPENn
Capture Function Enable Bits
Each bit n controls the corresponding PWM channel n.
0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
1 = Capture function Enabled. Capture latched the PWM counter value when detected
rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT
(Falling latch).