M451
May. 4, 2018
Page
965
of
1006
Rev.2.08
M4
51
S
E
RI
E
S
T
E
CH
NICA
L RE
F
E
R
E
NC
E
M
A
NU
A
L
A/D Status Register 0 (EADC_STATUS0)
Register
Offset
R/W
Description
Reset Value
EADC_STATUS0
0xF0
R
A/D Status Register 0
0x0000_0000
31
30
29
28
27
26
25
24
OV[15:8]
23
22
21
20
19
18
17
16
OV[7:0]
15
14
13
12
11
10
9
8
VALID[15:8]
7
6
5
4
3
2
1
0
VALID[7:0]
Bits
Description
[31:16]
OV[15:0]
EADC_DAT0~15 Overrun Flag
It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~18).
[15:0]
VALID[15:0]
EADC_DAT0~15 Data Valid Flag
It is a mirror of VALID bit in sample module A/D result data register EADC_DATn.
(n=0~18).
