M451
May. 4, 2018
Page
314
of
1006
Rev.2.08
M4
51
S
E
RI
E
S
T
E
CH
NICA
L RE
F
E
R
E
NC
E
M
A
NU
A
L
It must be 2 KB page alignment
It must be 2 KB alignment
FMC_MPDAT0~FMC_MPDAT3 :
N/A
Read Unique ID
0x04
0x0000_0000
FMC_ISPDAT: Unique ID Word 0
FMC_MPDAT0~FMC_MPDAT3 :
N/A
0x0000_0004
FMC_ISPDAT: Unique ID Word 1
FMC_MPDAT0~FMC_MPDAT3 :
N/A
0x0000_0008
FMC_ISPDAT: Unique ID Word 2
FMC_MPDAT0~FMC_MPDAT3 :
N/A
Vector Remap
0x2E
Valid address in APROM or LDROM
It must be 512 bytes alignment
N/A
Table 6-10 ISP Command List
ISP Procedure
The FMC controller provides embedded flash memory read, erase and program operation.
Several control bits of FMC control register are write-protected, thus it is necessary to unlock
before setting.
After unlocking the protected register bits, user needs to set the FMC_ISPCTL control register to
decide to update LDROM, APROM or user configuration block, and then set ISPEN
(FMC_ISPCTL[0]) to enable ISP function.
Once the FMC_ISPCTL register is set properly, user can set FMC_ISPCMD (refer above ISP
command list) for specify operation. Set FMC_ISPADDR for target flash memory based on flash
memory organization. FMC_ISPDAT can be used to set the data to program or used to return the
read data according to FMC_ISPCMD.
