M451
May. 4, 2018
Page
758
of
1006
Rev.2.08
M4
51
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Transmit FIFO interrupt
In FIFO mode, if the valid data count of the transmit FIFO buffer is less than or equal to the
setting value of TXTH (SPI_FIFOCTL[30:28]), the transmit FIFO interrupt flag TXTHIF
(SPI_STATUS[18]) will be set to 1. The SPI controller will generate a transmit FIFO interrupt to
the system if the transmit FIFO interrupt enable bit, TXTHIEN (SPI_FIFOCTL[3]), is set to 1.
Receive FIFO interrupt
In FIFO mode, if the valid data count of the receive FIFO buffer is larger than the setting value of
RXTH (SPI_FIFOCTL[26:24]), the receive FIFO interrupt flag RXTHIF (SPI_STATUS[10]) will be
set to 1. The SPI controller will generate a receive FIFO interrupt to the system if the receive FIFO
interrupt enable bit, RXTHIEN (SPI_FIFOCTL[2]), is set to 1.
I
2
S Mode
6.16.5.11
The SPI1 and SPI2 controllers support I
2
S mode with PCM mode A, PCM mode B, MSB justified
and I
2
S data format. The I2S_LRCLK signal indicates which audio channel is in transferring. The
bit count of an audio channel is determined by WDWIDTH (SPI_I2SCTL[5:4]). The transfer
sequence is always first from the most significance bit, MSB. Data are read on rising clock edge
and are driven on falling clock edge of I2S_BCLK.
In I
2
S data format, the MSB is sent and latched on the second clock of an audio channel.
MSB
word N-1
right channel
word N
left channel
word N+1
right channel
I2S_BCLK
I2S_LRCLK
I2S_DI / I2S_DO
LSB
MSB
Figure 6.16-25 I
2
S Data Format Timing Diagram
