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Nuvoton ARM Cortex NuMicro M451 Series, Technical Reference Manual

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Nuvoton ARM Cortex NuMicro M451 Series Technical Reference Manual Download Page 854

M451 

May. 4, 2018 

Page 

854

 of 

1006

 

Rev.2.08 

M4
51
 S
E

RI
E

S

 T

E

CH

NICA

L RE

F

E

R

E

NC

E

 M
A

NU

A

L

 

Bits 

Description 

0 = This device as a host interrupt Disabled.

 

1 = This device as a host interrupt Enabled.

 

[6] 

PDEVIEN 

Act As Peripheral Interrupt Enable Bit 

If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted. 

0 = This device as a peripheral interrupt Disabled.

 

1 = This device as a peripheral interrupt Enabled.

 

[5] 

IDCHGIEN 

IDSTS Changed Interrupt Enable Bit 

If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or 
from low to high, a interrupt will be asserted. 

0 = Interrupt Disabled. 

1 = Interrupt Enabled. 

[4] 

GOIDLEIEN 

OTG Device Goes to IDLE State Interrupt Enable Bit 

0 = Interrupt Disabled. 

1 = Interrupt Enabled. 

Note:

 Going to idle state means going to a_idle or b_idle state. Please refer to A-device 

state diagram and B-device state diagram in OTG spec. 

[3] 

HNPFIEN 

HNP Fail Interrupt Enable Bit 

0 = Interrupt Disabled. 

1 = Interrupt Enabled.

 

[2] 

SRPFIEN 

SRP Fail Interrupt Enable Bit 

0 = Interrupt Disabled. 

1 = Interrupt Enabled. 

[1] 

VBEIEN 

VBUS Error Interrupt Enable Bit 

0 = Interrupt Disabled. 

1 = Interrupt Enabled. 

Note:

 VBUS error means going to a_vbus_err state. Please refer to A-device state 

diagram in OTG spec. 

[0] 

ROLECHGIEN 

Role (Host or Peripheral) Changed Interrupt Enable Bit 

0 = Interrupt Disabled. 

1 = Interrupt Enabled. 

 

 

Summary of Contents for ARM Cortex NuMicro M451 Series

Page 1: ...l property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based...

Page 2: ...37 4 2 5 NuMicro M451M Series M058S Pin Compatible LQFP64 Pin Diagram 38 4 2 6 NuMicro M452 USB Series LQFP48 Pin Diagram 39 4 2 7 NuMicro M452 USB Series LQFP64 Pin Diagram 41 4 2 8 NuMicro M452 USB...

Page 3: ...RAM Memory Organization 186 6 2 7 Register Map 190 6 2 8 Register Description 192 6 2 9 System Timer SysTick 231 6 2 10 Nested Vectored Interrupt Controller NVIC 235 6 2 11 System Control Register 258...

Page 4: ...358 6 6 6 Register Map 360 6 6 7 Register Description 363 PDMA Controller PDMA 378 6 7 6 7 1 Overview 378 6 7 2 Features 378 6 7 3 Block Diagram 378 6 7 4 Basic Configuration 379 6 7 5 Functional Des...

Page 5: ...T 547 6 11 6 11 1 Overview 547 6 11 2 Features 547 6 11 3 Block Diagram 547 6 11 4 Clock Control 548 6 11 5 Basic Configuration 548 6 11 6 Functional Description 548 6 11 7 Register Map 551 6 11 8 Reg...

Page 6: ...5 4 Block Diagram 685 6 15 5 Functional Description 685 6 15 6 Register Map 719 6 15 7 Register Description 720 Serial Peripheral Interface SPI 740 6 16 6 16 1 Overview 740 6 16 2 Features 740 6 16 3...

Page 7: ...ister Map 849 6 19 7 Register Description 850 Controller Area Network CAN 858 6 20 6 20 1 Overview 858 6 20 2 Features 858 6 20 3 Basic Configuration 858 6 20 4 Block Diagram 858 6 20 5 Functional Des...

Page 8: ...n 974 6 23 6 Register Map 978 6 23 7 Register Description 979 Analog Comparator Controller ACMP 986 6 24 6 24 1 Overview 986 6 24 2 Features 986 6 24 3 Block Diagram 987 6 24 4 Basic Configuration 988...

Page 9: ...nly 43 Figure 4 2 11 NuMicro M451 CAN Series CAN USB LQFP 48 pin Diagram M453LG M453LE Device Only 44 Figure 4 2 12 NuMicro M451 CAN Series CAN USB LQFP 48 pin Diagram M453LD M453LC Device Only 45 Fig...

Page 10: ...ocedure Example 315 Figure 6 4 10 ISP 32 bit Programming Procedure 317 Figure 6 4 11 ISP 64 bit Programming Procedure 317 Figure 6 4 12 Multi word Programming Time 318 Figure 6 4 13 Firmware in SRAM f...

Page 11: ...gure 6 9 9 PWM Up Down Counter Type 442 Figure 6 9 10 PWM CMPDAT Events in Up Down Counter Type 443 Figure 6 9 11 PWM Double Buffering Illustration 444 Figure 6 9 12 Period Loading in Up Count Mode 44...

Page 12: ...Figure 6 9 43 Capture PDMA Operation Waveform of Channel 0 469 Figure 6 10 1 Watchdog Timer Block Diagram 540 Figure 6 10 2 Watchdog Timer Clock Control 541 Figure 6 10 3 Watchdog Timer Time out Inter...

Page 13: ...re 6 14 8 Initial Character TS 653 Figure 6 14 9 SC Error Signal 653 Figure 6 14 10 Transmit Direction Block Guard Time Operation 655 Figure 6 14 11 Receive Direction Block Guard Time Operation 656 Fi...

Page 14: ...Mode System Architecture 748 Figure 6 16 12 Two Bit Transfer Mode Timing Master Mode 749 Figure 6 16 13 Bit Sequence of Dual Output Mode 750 Figure 6 16 14 Bit Sequence of Dual Input Mode 750 Figure...

Page 15: ...a FIFO Buffer 870 Figure 6 20 7 Bit Timing 872 Figure 6 20 8 Propagation Time Segment 873 Figure 6 20 9 Synchronization on late and early Edges 875 Figure 6 20 10 Filtering of Short Dominant Spikes 8...

Page 16: ...Software Write Trigger 975 Figure 6 23 4 DAC Conversion Started by Hardware Trigger Event 975 Figure 6 23 5 DAC PDMA Underrun Condition Example 976 Figure 6 23 6 DAC Continuous Conversion with Softwar...

Page 17: ...Up Counter 450 Table 6 15 PWM Pulse Generation Event Priority for Down Counter 451 Table 6 16 PWM Pulse Generation Event Priority for Up Down Counter 451 Table 6 17 Watchdog Timer Time out Interval Pe...

Page 18: ...Transmit Object 867 Table 6 37 Initialization of a Receive Object 868 Table 6 38 CAN Bit Time Parameters 872 Table 6 39 CAN Register Map for Each Bit Function 886 Table 6 40 Last Error Code 891 Table...

Page 19: ...hannel 12 bit ADC with 1 MSPS conversion rate built in reference voltage VREF for circuit generation 12 bit DAC two analog comparators and temperature detectors The M451 series provides two special de...

Page 20: ...1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL Security Alarm System Power Metering Portable Data Collector Portable RFID Reader System Supervisors Smart Card Reader Printer Bar Code Scanner Mo...

Page 21: ...yte half word and word access Supports exception NMI generated once a parity check error occurs Supports PDMA mode PDMA Peripheral DMA Supports 12 8 independent configurable channels for automatic dat...

Page 22: ...er down or Idle mode Interrupt or reset selectable on watchdog time out Window Watchdog Timer Supports multiple clock sources from HCLK 2048 default selection and LIRC Window set by 6 bit counter with...

Page 23: ...it time out counters for Answer to Request ATR and waiting times processing Supports auto inverse convention function Supports stop clock level and clock stop clock keep function Supports transmitter...

Page 24: ...devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer Programmable clocks allow ve...

Page 25: ...input Supports PDMA transfer DAC Supports a 12 bit voltage type DAC Rail to rail settle time 8us External reference voltage VREF Max output voltage AVDD 0 2V at buffer mode Conversion started by soft...

Page 26: ...V 3 7 V 2 7 V 2 2 V Supports Brown out Interrupt and Reset option Low Voltage Reset Threshold voltage levels 2 0 V Operating Temperature 40 105 Packages All Green package RoHS LQFP 100 pin 14mm x 14m...

Page 27: ...troller FPU Floating point Unit GPIO General Purpose Input Output HCLK The Clock of Advanced High Performance Bus HIRC 22 1184 MHz Internal High Speed RC Oscillator HXT 4 20 MHz External High Speed Cr...

Page 28: ...ENCE MANUAL SPS Samples per Second TDES Triple Data Encryption Standard TMR Timer Controller UART Universal Asynchronous Receiver Transmitter UCID Unique Customer ID USB Universal Serial Bus WDT Watch...

Page 29: ...patible 2 USB Series 3 CAN CAN USB Series Flash ROM C 40KB D 72KB E 128KB G 256KB Temperature Reserved SRAM Size 3 16KB 6 32KB Package Type L LQFP 48 7x7mm S LQFP 64 7x7mm R LQFP 64 10x10mm V LQFP 100...

Page 30: ...39 4 3 1 1 3 2 2 2 12 2 8 ch LQFP 48 M451RG6AE 256 32 4 53 4 4 1 1 3 2 2 2 12 2 12 ch LQFP 64 M451RE6AE 128 32 4 53 4 4 1 1 3 2 2 2 12 2 12 ch LQFP 64 M451VG6AE 256 32 4 85 4 4 1 1 3 2 2 2 12 2 16 ch...

Page 31: ...N LIN M451MLG6A E 256 32 4 42 4 3 1 1 3 2 2 2 12 2 9 ch LQFP 48 M451MLE6A E 128 32 4 42 4 3 1 1 3 2 2 2 12 2 9 ch LQFP 48 M451MLD3A E 72 16 4 42 4 4 1 1 2 2 2 1 12 2 11 ch LQFP 48 M451MLC3A E 40 16 4...

Page 32: ...28 32 4 34 4 3 1 1 3 2 2 1 OTG 10 2 8 ch LQFP 48 M452RG6AE 256 32 4 48 4 4 1 1 3 2 2 2 OTG 12 2 12 ch LQFP 64 M452RE6AE 128 32 4 48 4 4 1 1 3 2 2 2 OTG 12 2 12 ch LQFP 64 M452VG6AE 256 32 4 80 4 4 1 1...

Page 33: ...1 8 ch LQFP 48 M453RG6AE 256 32 4 48 4 4 1 1 3 2 2 2 OTG 12 2 1 12 ch LQFP 64 M453RE6AE 128 32 4 48 4 4 1 1 3 2 2 2 OTG 12 2 1 12 ch LQFP 64 M453VG6AE 256 32 4 80 4 4 1 1 3 2 2 2 OTG 12 2 1 16 ch LQFP...

Page 34: ...LVIO PE 11 LVIO PA 3 PC 1 PC 0 LDO_CAP VSS PF 4 XT1_IN PF 3 XT1_OUT PD 7 PF 2 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 PE 10 LVIO LQFP 48 pin...

Page 35: ...19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 LQFP 64 pin PE 0 PC 4...

Page 36: ...P VDD VSS PF 4 XT1_IN PF 3 XT1_OUT PD 7 PD 15 PD 14 PD 13 PD 12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 37: ...5 PA 6 PA 3 PC 1 PC 0 LDO_CAP VSS PF 4 XT1_IN PF 3 XT1_OUT PD 7 PD 6 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 PA 7 LQFP 48 pin PD 2 PD 3 PD 4...

Page 38: ..._OUT PD 7 PC 13 PC 12 PC 11 PC 10 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 37 38 39 40 41 42 4...

Page 39: ...1 PC 0 LDO_CAP VSS PF 4 XT1_IN PF 3 XT1_OUT PD 7 PF 2 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 PE 10 LVIO LQFP 48 pin PD 2 PD 3 V BAT PE 0 PC...

Page 40: ...XT1_IN PF 3 XT1_OUT PD 7 PF 2 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 PE 10 LVIO LQFP 48 pin PD 2 PD 3 V BAT PE 0 PC 4 PC 3 PC 2 26 27 28 29...

Page 41: ...IO PE 8 LVIO PA 3 PB 4 PB 8 PB 11 PC 1 PC 0 LDO_CAP VDD VSS PF 4 XT1_IN PF 3 XT1_OUT PD 7 PD 15 PD 14 PD 13 PD 12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52...

Page 42: ...8 PB 11 PC 1 PC 0 LDO_CAP VDD VSS PF 4 XT1_IN PF 3 XT1_OUT PD 7 PD 15 PD 14 PD 13 PD 12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 16 15 14 13 12...

Page 43: ...0 PC 9 LDO_CAP VDD VSS PF 4 XT1_IN PF 3 XT1_OUT PD 7 PD 15 PD 14 PD 13 PD 12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 16 15 14 13 12 11 10 9 8 7...

Page 44: ...1 PC 0 LDO_CAP VSS PF 4 XT1_IN PF 3 XT1_OUT PD 7 PF 2 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 PE 10 LVIO LQFP 48 pin PD 2 PD 3 V BAT PE 0 PC...

Page 45: ..._IN PF 3 XT1_OUT PD 7 PF 2 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 PE 10 LVIO LQFP 48 pin PD 2 PD 3 V BAT PE 0 PC 4 PC 3 PC 2 26 27 28 29 30...

Page 46: ...IO PE 8 LVIO PA 3 PB 4 PB 8 PB 11 PC 1 PC 0 LDO_CAP VDD VSS PF 4 XT1_IN PF 3 XT1_OUT PD 7 PD 15 PD 14 PD 13 PD 12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52...

Page 47: ...B 11 PC 1 PC 0 LDO_CAP VDD VSS PF 4 XT1_IN PF 3 XT1_OUT PD 7 PD 15 PD 14 PD 13 PD 12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 16 15 14 13 12 11 1...

Page 48: ...0 PC 9 LDO_CAP VDD VSS PF 4 XT1_IN PF 3 XT1_OUT PD 7 PD 15 PD 14 PD 13 PD 12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 16 15 14 13 12 11 10 9 8 7...

Page 49: ...31 32 33 34 35 36 37 38 39 40 41 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 PA 7 PA 9 LQFP 100 pin 25 24 2...

Page 50: ...I O MFP2 SPI0 1st MISO Master In Slave Out pin SPI1_MISO I O MFP3 SPI1 MISO Master In Slave Out pin ACMP0_P1 A MFP5 Comparator0 positive input pin EBI_AD5 I O MFP7 EBI address data bus bit 5 3 PB 7 I...

Page 51: ...put pin INT0 I MFP8 External interrupt0 input pin 9 PD 3 I O MFP0 General purpose digital I O pin T2 I O MFP1 Timer2 event counter input toggle output T1_EXT I MFP3 Timer1 external capture input ACMP1...

Page 52: ...UART2 PWM0_CH0 I O MFP6 PWM0 output capture input EBI_AD8 I O MFP7 EBI address data bus bit 8 INT2 I MFP8 External interrupt2 input pin UART3_TXD O MFP9 Data transmitter output pin for UART3 M45xD M45...

Page 53: ...put capture input EBI_nCS1 O MFP7 EBI chip select 1 enable output pin INT4 I MFP8 External interrupt4 input pin 25 PC 5 I O MFP0 General purpose digital I O pin SPI2_I2SMCLK O MFP2 I2S2 master clock o...

Page 54: ..._RST O MFP5 SmartCard reset pin SPI1_I2SMCLK O MFP9 I2S1 master clock output pin M45xD M45xC Only PWM1_BRAKE1 I MFP10 PWM1 break input 1 M45xD M45xC Only T2 I O MFP11 Timer2 event counter input toggle...

Page 55: ...r input pin for UART0 UART0_nRTS O MFP3 Request to Send output pin for UART0 I2C0_SCL I O MFP4 I2C0 clock pin SC0_PWR O MFP5 SmartCard power pin PWM1_CH2 I O MFP6 PWM1 output capture input EBI_AD3 I O...

Page 56: ...SPI0 2nd MOSI Master Out Slave In pin UART2_RXD I MFP3 Data receiver input pin for UART2 T2 I O MFP4 Timer2 event counter input toggle output DAC A MFP5 DAC analog output EBI_nWRL O MFP7 EBI low byte...

Page 57: ...smitter output pin for UART1 UART3_TXD O MFP9 Data transmitter output pin for UART3 M45xD M45xC Only T0_EXT I MFP11 Timer0 external capture input M45xD M45xC Only 48 PB 4 I O MFP0 General purpose digi...

Page 58: ...r input pin for UART2 M45xD M45xC Only 3 PB 6 I O MFP0 General purpose digital I O pin EADC_CH14 A MFP1 EADC analog input channel 14 SPI0_MISO0 I O MFP2 SPI0 1st MISO Master In Slave Out pin SPI1_MISO...

Page 59: ...ger input pin UART0_TXD O MFP3 Data transmitter output pin for UART0 ACMP1_P2 A MFP5 Comparator1 positive input pin T0 I O MFP6 Timer0event counter input toggle output EBI_nRD O MFP7 EBI read enable o...

Page 60: ..._CH1 I O MFP6 PWM1 output capture input EBI_ADR17 O MFP7 EBI address bus bit 17 19 PD 14 I O MFP0 General purpose digital I O pin SPI2_MISO I O MFP2 SPI2 MISO Master In Slave Out pin M45xG M45xE Only...

Page 61: ...FP8 External interrupt2 input pin UART3_TXD O MFP9 Data transmitter output pin for UART3 M45xD M45xC Only T3_EXT I MFP11 Timer3 external capture input M45xD M45xC Only 28 PC 1 I O MFP0 General purpose...

Page 62: ...pt4 input pin 33 PC 5 I O MFP0 General purpose digital I O pin SPI2_I2SMCLK O MFP2 I2S2 master clock output pin M45xG M45xE Only PWM0_CH5 I O MFP6 PWM0 output capture input EBI_AD13 I O MFP7 EBI addre...

Page 63: ...4 I O MFP7 EBI address data bus bit 4 42 PE 8 I O MFP0 General purpose digital I O pin UART1_TXD O MFP1 Data transmitter output pin for UART1 SPI0_MISO1 I O MFP2 SPI0 2nd MISO Master In Slave Out pin...

Page 64: ...RT3 M45xD M45xC Only I2C1_SDA I O MFP11 I2C1 data input output pin M45xD M45xC Only 46 PE 12 I O MFP0 General purpose digital I O pin SPI1_SS I O MFP1 SPI1 slave select pin SPI0_SS I O MFP2 SPI0 slave...

Page 65: ...FP3 Data transmitter output pin for UART1 SC0_CLK O MFP5 SmartCard clock pin PWM1_CH5 I O MFP6 PWM1 output capture input EBI_AD0 I O MFP7 EBI address data bus bit 0 INT0 I MFP8 External interrupt0 inp...

Page 66: ...5xC Only T2_EXT I MFP11 Timer2 external capture input M45xD M45xC Only 60 PB 3 I O MFP0 General purpose digital I O pin EADC_CH3 A MFP1 EADC analog input channel 3 SPI0_MISO0 I O MFP2 SPI0 1st MISO Ma...

Page 67: ...FP Description UART1_nRTS O MFP4 Request to Send output pin for UART1 PWM0_CH2 I O MFP6 PWM0 output capture input 63 PB 11 I O MFP0 General purpose digital I O pin EADC_CH8 A MFP1 EADC analog input ch...

Page 68: ...SPI0_MOSI0 I O MFP2 SPI0 1st MOSI Master Out Slave In pin SPI1_MOSI I O MFP3 SPI1 MOSI Master Out Slave In pin ACMP0_P2 A MFP5 Comparator0 positive input pin EBI_AD6 I O MFP7 EBI address data bus bit...

Page 69: ...hip select 0 enable output pin 14 PD 9 I O MFP0 General purpose digital I O pin EADC_CH10 A MFP1 EADC analog input channel 10 M45xD M45xC Only ACMP1_P3 A MFP5 Comparator1 positive input pin EBI_ALE O...

Page 70: ...1 I MFP5 PWM0 break input 1 T1 I O MFP6 Timer1 event counter input toggle output 20 PE 3 I O MFP0 General purpose digital I O pin SPI1_MOSI I O MFP2 SPI1 MOSI Master Out Slave In pin PWM0_CH3 I O MFP6...

Page 71: ...nput EBI_ADR17 O MFP7 EBI address bus bit 17 30 PD 14 I O MFP0 General purpose digital I O pin SPI2_MISO I O MFP2 SPI2 MISO Master In Slave Out pin M45xG M45xE Only UART3_nCTS I MFP3 Clear to Send inp...

Page 72: ...1 output capture input 40 PC 11 I O MFP0 General purpose digital I O pin SPI2_MISO I O MFP2 SPI2 MISO Master In Slave Out pin M45xG M45xE Only PWM1_CH2 I O MFP6 PWM1 output capture input 41 PC 12 I O...

Page 73: ...digital I O pin SPI2_MOSI I O MFP2 SPI2 MOSI Master Out Slave In pin M45xG M45xE Only UART2_RXD I MFP3 Data receiver input pin for UART2 PWM0_CH3 I O MFP6 PWM0 output capture input EBI_AD11 I O MFP7 E...

Page 74: ...y 53 PE 4 I O MFP0 General purpose digital I O pin I2C1_SCL I O MFP3 I2C1 clock pin SC0_PWR O MFP5 SmartCard power pin PWM1_BRAKE0 I MFP6 PWM1 break input 0 EBI_nCS0 O MFP7 EBI chip select 0 enable ou...

Page 75: ...I O pin SPI1_MOSI I O MFP2 SPI1 MOSI Master Out Slave In pin T2_EXT I MFP3 Timer2 external capture input EBI_AD5 I O MFP7 EBI address data bus bit 5 65 PA 4 I O MFP0 General purpose digital I O pin SP...

Page 76: ...MBALTER pin SC0_DAT I O MFP5 SmartCard data pin UART3_TXD O MFP9 Data transmitter output pin for UART3 M45xD M45xC Only I2C1_SCL I O MFP11 I2C1 clock pin M45xD M45xC Only 72 PE 11 I O MFP0 General pur...

Page 77: ...bit 3 80 PA 2 I O MFP0 General purpose digital I O pin UART0_TXD O MFP2 Data transmitter output pin for UART0 UART0_nCTS I MFP3 Clear to Send input pin for UART0 I2C0_SDA I O MFP4 I2C0 data input outp...

Page 78: ...A MFP0 Power supply for internal analog circuit 90 VREF I MFP0 Voltage reference input for ADC Note This pin needs to be connected with a 1uF capacitor 91 PB 0 I O MFP0 General purpose digital I O pi...

Page 79: ...ly 95 PB 4 I O MFP0 General purpose digital I O pin EADC_CH4 A MFP1 EADC analog input channel 4 SPI0_SS I O MFP2 SPI0 slave select pin SPI1_SS I O MFP3 SPI1 slave select pin UART1_nCTS I MFP4 Clear to...

Page 80: ...M451 May 4 2018 Page 80 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL Pin No Pin Name Type MFP Description EADC_CH9 A MFP1 EADC analog input channel 9...

Page 81: ...SPI1_MISO I O MFP3 SPI1 MISO Master In Slave Out pin ACMP0_P1 A MFP5 Comparator0 positive input pin EBI_AD5 I O MFP7 EBI address data bus bit 5 3 PB 7 I O MFP0 General purpose digital I O pin EADC_CH1...

Page 82: ...in 9 PD 3 I O MFP0 General purpose digital I O pin T2 I O MFP1 Timer2 event counter input toggle output T1_EXT I MFP3 Timer1 external capture input ACMP1_P0 A MFP5 Comparator1 positive input pin PWM0_...

Page 83: ...nal 4 20 MHz high speed crystal output pin I2C1_SCL I O MFP3 I2C1 clock pin 16 PF 4 I O MFP0 General purpose digital I O pin XT1_IN I MFP1 External 4 20 MHz high speed crystal input pin I2C1_SDA I O M...

Page 84: ...input EBI_AD11 I O MFP7 EBI address data bus bit 11 23 PC 4 I O MFP0 General purpose digital I O pin SPI2_MISO I O MFP2 SPI2 MISO Master In Slave Out pin M45xG M45xE Only I2C1_SCL I O MFP3 I2C1 clock...

Page 85: ...7 EBI chip select 0 enable output pin INT0 I MFP8 External interrupt0 input pin 29 PE 5 I O MFP0 General purpose digital I O pin I2C1_SDA I O MFP3 I2C1 data input output pin SC0_RST O MFP5 SmartCard r...

Page 86: ...ck pin SC0_PWR O MFP5 SmartCard power pin PWM1_CH2 I O MFP6 PWM1 output capture input EBI_AD3 I O MFP7 EBI address data bus bit 3 38 PA 2 I O MFP0 General purpose digital I O pin UART0_TXD O MFP2 Data...

Page 87: ...e output pin INT1 I MFP8 External interrupt1 input pin 44 PB 1 I O MFP0 General purpose digital I O pin EADC_CH1 A MFP1 EADC analog input channel 1 SPI0_MISO1 I O MFP2 SPI0 2nd MISO Master In Slave Ou...

Page 88: ...I O pin EADC_CH4 A MFP1 EADC analog input channel 4 SPI0_SS I O MFP2 SPI0 slave select pin SPI1_SS I O MFP3 SPI1 slave select pin UART1_nCTS I MFP4 Clear to Send input pin for UART1 ACMP0_N A MFP5 Co...

Page 89: ...SPI1_MISO I O MFP3 SPI1 MISO Master In Slave Out pin ACMP0_P1 A MFP5 Comparator0 positive input pin EBI_AD5 I O MFP7 EBI address data bus bit 5 3 PB 7 I O MFP0 General purpose digital I O pin EADC_CH1...

Page 90: ...Timer0event counter input toggle output EBI_nRD O MFP7 EBI read enable output pin 11 PD 2 I O MFP0 General purpose digital I O pin STADC I MFP1 ADC external trigger input T0_EXT I MFP3 Timer0 external...

Page 91: ...pin 17 PD 7 I O MFP0 General purpose digital I O pin PWM0_SYNC_IN I MFP3 PWM0 counter synchronous trigger input pin T1 I O MFP4 Timer1 event counter input toggle output ACMP0_O O MFP5 Comparator0 out...

Page 92: ...0_CH0 I O MFP6 PWM0 output capture input EBI_AD8 I O MFP7 EBI address data bus bit 8 INT2 I MFP8 External interrupt2 input pin UART3_TXD O MFP9 Data transmitter output pin for UART3 M45xD M45xC Only T...

Page 93: ...0 output capture input EBI_nCS1 O MFP7 EBI chip select 1 enable output pin INT4 I MFP8 External interrupt4 input pin 33 PC 5 I O MFP0 General purpose digital I O pin SPI2_I2SMCLK O MFP2 I2S2 master cl...

Page 94: ...0 General purpose digital I O pin UART3_TXD O MFP3 Data transmitter output pin for UART3 41 PA 9 I O MFP0 General purpose digital I O pin UART3_RXD I MFP3 Data receiver input pin for UART3 42 PA 10 I...

Page 95: ...PA 2 I O MFP0 General purpose digital I O pin UART0_TXD O MFP2 Data transmitter output pin for UART0 UART0_nCTS I MFP3 Clear to Send input pin for UART0 I2C0_SDA I O MFP4 I2C0 data input output pin S...

Page 96: ...EADC analog input SPI0_MOSI1 I O MFP2 SPI0 2nd MOSI Master Out Slave In pin UART2_RXD I MFP3 Data receiver input pin for UART2 T2 I O MFP4 Timer2 event counter input toggle output DAC A MFP5 DAC analo...

Page 97: ...Only T0_EXT I MFP11 Timer0 external capture input M45xD M45xC Only 63 PB 4 I O MFP0 General purpose digital I O pin EADC_CH4 A MFP1 EADC analog input channel 4 SPI0_SS I O MFP2 SPI0 slave select pin S...

Page 98: ...I O MFP3 SPI1 MISO Master In Slave Out pin ACMP0_P1 A MFP5 Comparator0 positive input pin EBI_AD5 I O MFP7 EBI address data bus bit 5 3 PB 7 I O MFP0 General purpose digital I O pin EADC_CH15 A MFP1...

Page 99: ...I O pin T2 I O MFP1 Timer2 event counter input toggle output T1_EXT I MFP3 Timer1 external capture input ACMP1_P0 A MFP5 Comparator1 positive input pin PWM0_BRAKE1 I MFP6 PWM0 break input 1 EBI_MCLK...

Page 100: ...address data bus bit 8 INT2 I MFP8 External interrupt2 input pin UART3_TXD O MFP9 Data transmitter output pin for UART3 M45xD M45xC Only T3_EXT I MFP11 Timer3 external capture input M45xD M45xC Only...

Page 101: ...2 external capture input SC0_CD I MFP5 SmartCard card detect pin PWM0_CH0 I O MFP6 PWM0 output capture input EBI_nCS1 O MFP7 EBI chip select 1 enable output pin INT4 I MFP8 External interrupt4 input p...

Page 102: ...ART1 I2C0_SDA I O MFP4 I2C0 data input output pin 31 VDDIO A MFP0 Power supply for PE 10 PE 13 32 USB_VBUS A MFP0 Power supply from USB host or HUB 33 USB_D I MFP0 USB differential signal D 34 USB_D I...

Page 103: ...FP1 Clear to Send input pin for UART1 UART1_TXD O MFP3 Data transmitter output pin for UART1 SC0_CLK O MFP5 SmartCard clock pin PWM1_CH5 I O MFP6 PWM1 output capture input EBI_AD0 I O MFP7 EBI address...

Page 104: ...MFP9 Data receiver input pin for UART3 M45xD M45xC Only T2_EXT I MFP11 Timer2 external capture input M45xD M45xC Only 47 PB 3 I O MFP0 General purpose digital I O pin EADC_CH3 A MFP1 EADC analog input...

Page 105: ...r input pin for UART2 M45xD M45xC Only 3 PB 6 I O MFP0 General purpose digital I O pin EADC_CH14 A MFP1 EADC analog input channel 14 SPI0_MISO0 I O MFP2 SPI0 1st MISO Master In Slave Out pin SPI1_MISO...

Page 106: ...ger input pin UART0_TXD O MFP3 Data transmitter output pin for UART0 ACMP1_P2 A MFP5 Comparator1 positive input pin T0 I O MFP6 Timer0event counter input toggle output EBI_nRD O MFP7 EBI read enable o...

Page 107: ..._CH1 I O MFP6 PWM1 output capture input EBI_ADR17 O MFP7 EBI address bus bit 17 19 PD 14 I O MFP0 General purpose digital I O pin SPI2_MISO I O MFP2 SPI2 MISO Master In Slave Out pin M45xG M45xE Only...

Page 108: ...interrupt2 input pin UART3_TXD O MFP9 Data transmitter output pin for UART3 M45xD M45xC Only T3_EXT I MFP11 Timer3 external capture input M45xD M45xC Only 28 PC 1 I O MFP0 General purpose digital I O...

Page 109: ...eral purpose digital I O pin I2C1_SMBAL O MFP3 I2C1 SMBus SMBALTER pin ACMP1_O O MFP5 Comparator1 output PWM1_CH0 I O MFP6 PWM1 output capture input EBI_AD14 I O MFP7 EBI address data bus bit 14 UART0...

Page 110: ...SPI0_MISO0 I O MFP2 SPI0 1st MISO Master In Slave Out pin UART1_nCTS I MFP3 Clear to Send input pin for UART1 I2C0_SMBAL O MFP4 I2C0 SMBus SMBALTER pin SC0_DAT I O MFP5 SmartCard data pin UART3_TXD O...

Page 111: ...USB_VBUS_ST I MFP1 USB external VBUS regulator status pin M45xG M45xE Only UART0_RXD I MFP2 Data receiver input pin for UART0 UART0_nRTS O MFP3 Request to Send output pin for UART0 I2C0_SCL I O MFP4...

Page 112: ...I MFP0 Voltage reference input for ADC Note This pin needs to be connected with a 1uF capacitor 57 PB 0 I O MFP0 General purpose digital I O pin EADC_CH0 A MFP1 EADC analog input SPI0_MOSI1 I O MFP2...

Page 113: ...M45xC Only T0_EXT I MFP11 Timer0 external capture input M45xD M45xC Only 61 PB 4 I O MFP0 General purpose digital I O pin EADC_CH4 A MFP1 EADC analog input channel 4 SPI0_SS I O MFP2 SPI0 slave select...

Page 114: ...General purpose digital I O pin EADC_CH13 A MFP1 EADC analog input channel 13 SPI0_MOSI0 I O MFP2 SPI0 1st MOSI Master Out Slave In pin SPI1_MOSI I O MFP3 SPI1 MOSI Master Out Slave In pin ACMP0_P2 A...

Page 115: ...eneral purpose digital I O pin EADC_CH7 A MFP1 EADC analog input channel 7 M45xD M45xC Only EBI_nCS0 O MFP7 EBI chip select 0 enable output pin 14 PD 9 I O MFP0 General purpose digital I O pin EADC_CH...

Page 116: ...PI1_MISO I O MFP2 SPI1 MISO Master In Slave Out pin I2C0_SCL I O MFP3 I2C0 clock pin PWM0_BRAKE1 I MFP5 PWM0 break input 1 T1 I O MFP6 Timer1 event counter input toggle output 20 PE 3 I O MFP0 General...

Page 117: ...address bus bit 16 29 PD 13 I O MFP0 General purpose digital I O pin SPI2_MOSI I O MFP2 SPI2 MOSI Master Out Slave In pin M45xG M45xE Only UART3_RXD I MFP3 Data receiver input pin for UART3 PWM1_CH1 I...

Page 118: ...ter clock output pin M45xG M45xE Only PWM1_CH0 I O MFP6 PWM1 output capture input M45xG M45xE Only NC Not connected M45xD M45xC Only 39 PC 10 I O MFP0 General purpose digital I O pin SPI2_MOSI I O MFP...

Page 119: ...MFP0 General purpose digital I O pin SPI2_SS I MFP2 SPI2 slave select pin M45xG M45xE Only UART2_TXD O MFP3 Data transmitter output pin for UART2 ACMP1_O O MFP5 Comparator1 output PWM0_CH2 I O MFP6 PW...

Page 120: ...omparator1 output PWM1_CH0 I O MFP6 PWM1 output capture input EBI_AD14 I O MFP7 EBI address data bus bit 14 UART0_TXD O MFP9 Data transmitter output pin for UART0 M45xD M45xC Only 52 PC 7 I O MFP0 Gen...

Page 121: ...ve Out pin T1_EXT I MFP3 Timer1 external capture input EBI_AD6 I O MFP7 EBI address data bus bit 6 61 PA 5 I O MFP0 General purpose digital I O pin SPI1_MOSI I O MFP2 SPI1 MOSI Master Out Slave In pin...

Page 122: ...I O MFP1 SPI1 MISO Master In Slave Out pin SPI0_MISO0 I O MFP2 SPI0 1st MISO Master In Slave Out pin UART1_nCTS I MFP3 Clear to Send input pin for UART1 I2C0_SMBAL O MFP4 I2C0 SMBus SMBALTER pin SC0_D...

Page 123: ...O MFP0 General purpose digital I O pin M45xG M45xE Only PWM1_CH1 I O MFP6 PWM1 output capture input M45xG M45xE Only NC Not connected M45xD M45xC Only 79 PA 3 I O MFP0 General purpose digital I O pin...

Page 124: ...General purpose digital I O pin SPI1_I2SMCLK O MFP2 I2S1 master clock output pin 84 PA 13 I O MFP0 General purpose digital I O pin 85 PA 14 I O MFP0 General purpose digital I O pin UART2_nCTS I MFP3...

Page 125: ...UART1_RXD I MFP4 Data receiver input pin for UART1 SC0_CD I MFP5 SmartCard card detect pin UART3_RXD I MFP9 Data receiver input pin for UART3 M45xD M45xC Only T2_EXT I MFP11 Timer2 external capture in...

Page 126: ...FP6 PWM0 output capture input 97 PB 9 I O MFP0 General purpose digital I O pin M45xG M45xE Only EADC_CH6 A MFP1 EADC analog input channel 6 M45xG M45xE Only NC Not connected M45xD M45xC Only 98 PB 10...

Page 127: ..._MISO I O MFP3 SPI1 MISO Master In Slave Out pin ACMP0_P1 A MFP5 Comparator0 positive input pin EBI_AD5 I O MFP7 EBI address data bus bit 5 3 PB 7 I O MFP0 General purpose digital I O pin EADC_CH15 A...

Page 128: ...I O pin T2 I O MFP1 Timer2 event counter input toggle output T1_EXT I MFP3 Timer1 external capture input ACMP1_P0 A MFP5 Comparator1 positive input pin PWM0_BRAKE1 I MFP6 PWM0 break input 1 EBI_MCLK...

Page 129: ...re input EBI_AD8 I O MFP7 EBI address data bus bit 8 INT2 I MFP8 External interrupt2 input pin UART3_TXD O MFP9 Data transmitter output pin for UART3 M45xD M45xC Only T3_EXT I MFP11 Timer3 external ca...

Page 130: ...A I O MFP3 I2C1 data input output pin T2_EXT I MFP4 Timer2 external capture input SC0_CD I MFP5 SmartCard card detect pin PWM0_CH0 I O MFP6 PWM0 output capture input EBI_nCS1 O MFP7 EBI chip select 1...

Page 131: ...I MFP3 Data receiver input pin for UART1 I2C0_SDA I O MFP4 I2C0 data input output pin 31 VDDIO A MFP0 Power supply for PE 10 PE 13 32 USB_VBUS A MFP0 Power supply from USB host or HUB 33 USB_D I MFP0...

Page 132: ...t M45xD M45xC Only 40 PA 0 I O MFP0 General purpose digital I O pin UART1_nCTS I MFP1 Clear to Send input pin for UART1 UART1_TXD O MFP3 Data transmitter output pin for UART1 CAN0_RXD I MFP4 CAN bus r...

Page 133: ...UART1_RXD I MFP4 Data receiver input pin for UART1 SC0_CD I MFP5 SmartCard card detect pin UART3_RXD I MFP9 Data receiver input pin for UART3 M45xD M45xC Only T2_EXT I MFP11 Timer2 external capture in...

Page 134: ...M451 May 4 2018 Page 134 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL Pin No Pin Name Type MFP Description T1_EXT I MFP11 Timer1 external capture input M45xD M45xC Only...

Page 135: ...ceiver input pin for UART2 M45xD M45xC Only 3 PB 6 I O MFP0 General purpose digital I O pin EADC_CH14 A MFP1 EADC analog input channel 14 SPI0_MISO0 I O MFP2 SPI0 1st MISO Master In Slave Out pin SPI1...

Page 136: ...ger input pin UART0_TXD O MFP3 Data transmitter output pin for UART0 ACMP1_P2 A MFP5 Comparator1 positive input pin T0 I O MFP6 Timer0event counter input toggle output EBI_nRD O MFP7 EBI read enable o...

Page 137: ..._CH1 I O MFP6 PWM1 output capture input EBI_ADR17 O MFP7 EBI address bus bit 17 19 PD 14 I O MFP0 General purpose digital I O pin SPI2_MISO I O MFP2 SPI2 MISO Master In Slave Out pin M45xG M45xE Only...

Page 138: ...I_AD8 I O MFP7 EBI address data bus bit 8 INT2 I MFP8 External interrupt2 input pin UART3_TXD O MFP9 Data transmitter output pin for UART3 M45xD M45xC Only T3_EXT I MFP11 Timer3 external capture input...

Page 139: ...6 PWM0 output capture input EBI_AD13 I O MFP7 EBI address data bus bit 13 33 PC 6 I O MFP0 General purpose digital I O pin I2C1_SMBAL O MFP3 I2C1 SMBus SMBALTER pin ACMP1_O O MFP5 Comparator1 output P...

Page 140: ...urpose digital I O pin SPI1_MISO I O MFP1 SPI1 MISO Master In Slave Out pin SPI0_MISO0 I O MFP2 SPI0 1st MISO Master In Slave Out pin UART1_nCTS I MFP3 Clear to Send input pin for UART1 I2C0_SMBAL O M...

Page 141: ...be connected with a 1uF capacitor 49 PA 3 I O MFP0 General purpose digital I O pin USB_VBUS_ST I MFP1 USB external VBUS regulator status pin M45xG M45xE Only UART0_RXD I MFP2 Data receiver input pin f...

Page 142: ...digital circuit 54 VDD A MFP0 Power supply for I O ports and LDO source for internal PLL and digital function 55 AVDD A MFP0 Power supply for internal analog circuit 56 VREF I MFP0 Voltage reference...

Page 143: ...ransmitter output pin for UART1 UART3_TXD O MFP9 Data transmitter output pin for UART3 M45xD M45xC Only T0_EXT I MFP11 Timer0 external capture input M45xD M45xC Only 61 PB 4 I O MFP0 General purpose d...

Page 144: ...MFP0 General purpose digital I O pin EADC_CH13 A MFP1 EADC analog input channel 13 SPI0_MOSI0 I O MFP2 SPI0 1st MOSI Master Out Slave In pin SPI1_MOSI I O MFP3 SPI1 MOSI Master Out Slave In pin ACMP0_...

Page 145: ...eneral purpose digital I O pin EADC_CH7 A MFP1 EADC analog input channel 7 M45xD M45xC Only EBI_nCS0 O MFP7 EBI chip select 0 enable output pin 14 PD 9 I O MFP0 General purpose digital I O pin EADC_CH...

Page 146: ...PI1_MISO I O MFP2 SPI1 MISO Master In Slave Out pin I2C0_SCL I O MFP3 I2C0 clock pin PWM0_BRAKE1 I MFP5 PWM0 break input 1 T1 I O MFP6 Timer1 event counter input toggle output 20 PE 3 I O MFP0 General...

Page 147: ...address bus bit 16 29 PD 13 I O MFP0 General purpose digital I O pin SPI2_MOSI I O MFP2 SPI2 MOSI Master Out Slave In pin M45xG M45xE Only UART3_RXD I MFP3 Data receiver input pin for UART3 PWM1_CH1 I...

Page 148: ...ter clock output pin M45xG M45xE Only PWM1_CH0 I O MFP6 PWM1 output capture input M45xG M45xE Only NC Not connected M45xD M45xC Only 39 PC 10 I O MFP0 General purpose digital I O pin SPI2_MOSI I O MFP...

Page 149: ...bit 9 UART3_RXD I O MFP9 Data receiver input pin for UART3 M45xD M45xC Only 46 PC 2 I O MFP0 General purpose digital I O pin SPI2_SS I MFP2 SPI2 slave select pin M45xG M45xE Only UART2_TXD O MFP3 Data...

Page 150: ...FP0 General purpose digital I O pin I2C1_SMBAL O MFP3 I2C1 SMBus SMBALTER pin ACMP1_O O MFP5 Comparator1 output PWM1_CH0 I O MFP6 PWM1 output capture input EBI_AD14 I O MFP7 EBI address data bus bit 1...

Page 151: ...60 PA 6 I O MFP0 General purpose digital I O pin SPI1_MISO I O MFP2 SPI1 MISO Master In Slave Out pin T1_EXT I MFP3 Timer1 external capture input EBI_AD6 I O MFP7 EBI address data bus bit 6 61 PA 5 I...

Page 152: ...ggle output M45xD M45xC Only 68 PE 10 I O MFP0 General purpose digital I O pin SPI1_MISO I O MFP1 SPI1 MISO Master In Slave Out pin SPI0_MISO0 I O MFP2 SPI0 1st MISO Master In Slave Out pin UART1_nCTS...

Page 153: ...ut 3 3V decoupling pin Note This pin needs to be connected with a 1uF capacitor 78 PE 2 I O MFP0 General purpose digital I O pin M45xG M45xE Only PWM1_CH1 I O MFP6 PWM1 output capture input M45xG M45x...

Page 154: ...capture input EBI_AD0 I O MFP7 EBI address data bus bit 0 INT0 I MFP8 External interrupt0 input pin SPI1_I2SMCLK O MFP9 I2S1 master clock output pin M45xD M45xC Only 83 PA 12 I O MFP0 General purpose...

Page 155: ...unter synchronous trigger output pin EBI_nWRH O MFP7 EBI high byte write enable output pin 93 PB 2 I O MFP0 General purpose digital I O pin EADC_CH2 A MFP1 EADC analog input channel 2 SPI0_CLK I O MFP...

Page 156: ...gital I O pin EADC_CH5 A MFP1 EADC analog input channel 5 UART1_nRTS O MFP4 Request to Send output pin for UART1 PWM0_CH2 I O MFP6 PWM0 output capture input 97 PB 9 I O MFP0 General purpose digital I...

Page 157: ...omparator1 positive input pin ACMP1_P1 PD 2 MFP5 A Comparator1 positive input pin ACMP1_P2 PD 1 MFP5 A Comparator1 positive input pin ACMP1_P3 PD 9 MFP5 A Comparator1 positive input pin EADC EADC_CH0...

Page 158: ...ut CLKO PD 6 MFP1 O Clock Out CLKO PC 1 MFP1 O Clock Out CLKO PE 8 MFP9 O Clock Out M45xD M45xC Only DAC DAC PB 0 MFP5 A DAC analog output STDAC PC 1 MFP2 I DAC external trigger input EBI EBI_AD0 PA 0...

Page 159: ...O EBI chip select 0 enable output pin EBI_nCS1 PB 15 MFP7 O EBI chip select 1 enable output pin EBI_nCS1 PE 0 MFP7 O EBI chip select 1 enable output pin EBI_nRD PD 1 MFP7 O EBI read enable output pin...

Page 160: ...PI1_I2SMCLK PE 9 MFP9 O I2S1 master clock output pin M45xD M45xC Only SPI1_I2SMCLK PA 0 MFP9 O I2S1 master clock output pin M45xD M45xC Only I2S2 SPI2_I2SMCLK PC 9 MFP2 O I2S2 master clock output pin...

Page 161: ...PWM0 output capture input PWM0_SYNC_IN PD 1 MFP2 I PWM0 counter synchronous trigger input pin PWM0_SYNC_IN PD 7 MFP3 I PWM0 counter synchronous trigger input pin PWM0_SYNC_OUT PB 1 MFP6 O PWM0 counte...

Page 162: ...PE 5 MFP5 O SmartCard reset pin SC0_RST PE 9 MFP5 O SmartCard reset pin SC0_RST PA 2 MFP5 O SmartCard reset pin SC0_RST PB 1 MFP5 O SmartCard reset pin SPI0 SPI0_CLK PB 7 MFP2 I O SPI0 serial clock pi...

Page 163: ...PI1_SS PA 4 MFP2 I O SPI1 slave select pin SPI1_SS PE 12 MFP1 I O SPI1 slave select pin SPI1_SS PB 4 MFP3 I O SPI1 slave select pin SPI2 SPI2_CLK PD 15 MFP2 I O SPI2 serial clock pin M45xG M45xE Only...

Page 164: ...nt counter input toggle output T2 PB 0 MFP4 I O Timer2 event counter input toggle output T2 PE 9 MFP11 I O Timer2 event counter input toggle output M45xD M45xC Only T2_EXT PE 0 MFP4 I Timer2 external...

Page 165: ...ut pin for UART1 UART1_nRTS PE 11 MFP3 O Request to Send output pin for UART1 UART1_nRTS PA 1 MFP1 O Request to Send output pin for UART1 UART1_nRTS PB 8 MFP4 O Request to Send output pin for UART1 UA...

Page 166: ...d input pin for UART3 UART3_nRTS PD 15 MFP3 O Request to Send output pin for UART3 UART3_nRTS PA 11 MFP3 O Request to Send output pin for UART3 USB USB_VBUS_EN PC 4 MFP4 O USB external VBUS regulator...

Page 167: ...M451 May 4 2018 Page 167 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL 5 BLOCK DIAGRAM NuMicro M451 Block Diagram 5 1 Figure 5 1 1 NuMicro M45xG M45xE Block Diagram...

Page 168: ...M451 May 4 2018 Page 168 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL Figure 5 1 2 NuMicro M45xD M45xC Block Diagram...

Page 169: ...eption return can only be issued in Handler mode Thread mode is entered on Reset and can be entered as a result of an exception return The Cortex M4F is a processor with the same capability as the Cor...

Page 170: ...integrated with the processor core to achieve low latency interrupt processing Features include External interrupts Configurable from 1 to 240 the NuMicro M451 family configured with 64 interrupts Bit...

Page 171: ...ell ITM for support of printf style debugging Optional Trace Port Interface Unit TPIU for bridging to a Trace Port Analyzer TPA including Single Wire Output SWO mode Optional Embedded Trace Macrocell...

Page 172: ...6 2 2 System Reset The system reset can be issued by one of the events listed below These reset event flags can be read from SYS_RSTSTS register to determine the reset source Hardware reset can reset...

Page 173: ...0k ohm 5v Reset Pulse Width 2 system clocks nRESET VDD AVDD CHIP Reset CHIPRST SYS_IPRST0 0 CPU Reset CPURST SYS_IPRST0 1 CPU Lockup Reset MCU Reset SYSRSTREQ AIRCR 2 LVREN SYS_BODCTL 7 BODRSTEN SYS_B...

Page 174: ...eload from CONFIG0 BODVL SYS_BODCTL 2 1 BODRSTEN SYS_BODCTL 3 HXTEN CLK_PWRCTL 0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0...

Page 175: ...oad from CONFIG0 PGFF FMC_ISPSTS 5 0x0 0x0 0x0 VECMAP FMC_ISPSTS 23 9 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on...

Page 176: ...set waveform VDD VPOR Power on Reset 0 1V Figure 6 2 3 Power on Reset POR Waveform Low Voltage Reset LVR 6 2 2 3 If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bi...

Page 177: ...ing system operation When the AVDD voltage is lower than VBOD and the state keeps longer than De glitch time set by BODDGSEL SYS_BODCTL 10 8 chip will be reset The BOD reset will control the chip in r...

Page 178: ...failure of MCU after watchdog time out reset by checking WDTRF SYS_RSTSTS 2 CPU Lockup Reset M45xD M45xC Only 6 2 2 6 CPU enters lockup status after CPU produces hardfault at hardfault handler and chi...

Page 179: ...on Chip is in normal mode after system reset released CPU executes WFI instruction CPU sets sleep mode enable and power down enable and executes WFI instruction Wake up Sources N A All interrupts RTC...

Page 180: ...XT is on Normal Mode Idle Mode Power Down Mode HXT 4 20 MHz XTL ON ON Halt HIRC 12 16 MHz OSC ON ON Halt LXT 32768 Hz XTL ON ON ON OFF1 LIRC 10 kHz OSC ON ON ON OFF2 PLL ON ON Halt LDO ON ON ON CPU ON...

Page 181: ...RTC_INTSTS 2 UART RX Data wake up After software writes 1 to clear DATWKIF UARTx_INTSTS 17 nCTS wake up After software writes 1 to clear CTSWKIF UARTx_INTSTS 16 I2 C Falling edge in the I2C_SDA or I2C...

Page 182: ...uit still being enabled Please refer to M451 Errata for detailed description M45xD M45xC Only USB Transceiver AVDD AVSS V DD V SS VDD M45xG M45xE Only VBUS M45xD M45xC Only USB_D USB_D V BAT 22 1184 M...

Page 183: ...0x2000_3FFF SRAM0_BA SRAM Memory Space M45xG M45xE Only 0x2000_4000 0x2000_7FFF SRAM1_BA SRAM Memory Space M45xG M45xE Only 0x2000_8000 0x2000_BFFF Reserved Reserved 0x2000_C000 0x2000_FFFF Reserved R...

Page 184: ...Reserved Reserved 0x4005_D000 0x4005_DFFF Reserved Reserved 0x4006_0000 0x4006_0FFF SPI0_BA SPI0 Control Registers 0x4006_1000 0x4006_1FFF SPI1_BA SPI1 Control Registers 0x4006_2000 0x4006_2FFF SPI2_...

Page 185: ...x400B_0FFF Reserved Reserved 0x400B_1000 0x400B_1FFF Reserved Reserved 0x400C_0000 0x400C_0FFF USBD_BA USB Device Control Register 0x400E_0000 0x400E_0FFF Reserved Reserved 0x5008_0000 0x5008_0FFF Res...

Page 186: ...o banks SRAM bank0 and SRAM bank1 Each of these two banks has 8 KB address space and can be accessed simultaneously The SRAM bank0 supports parity error check to make sure chip operating more stable S...

Page 187: ...will enter hardfault if CPU accesses these illegal memory addresses The address of each bank is remapping from 0x2000_0000 to 0x1000_0000 CPU can read SRAM bank0 through 0x2000_0000 to 0x2000_3FFF or...

Page 188: ...0x1000_0000 CPU can read SRAM bank0 through 0x2000_0000 to 0x2000_1FFF or 0x1000_0000 to 0x1000_1FFF and read SRAM bank1 through 0x2000_2000 to 0x2000_3FFF or 0x1000_2000 to 0x1000_3FFF 512MB 0x2000_...

Page 189: ...UAL recode the address with parity error Chip will enter interrupt when SRAM parity error occurred if PERRIEN SYS_SRAM_INTCTL 0 is set to 1 When SRAM parity error occurred chip will stop detecting SRA...

Page 190: ...YS_GPA_MFPH SYS_BA 0x34 R W GPIOA High Byte Multiple Function Control Register 0x0000_0000 SYS_GPB_MFPL SYS_BA 0x38 R W GPIOB Low Byte Multiple Function Control Register 0x0000_0000 SYS_GPB_MFPH SYS_B...

Page 191: ...RCTCTL SYS_BA 0xF0 R W HIRC Trim Control Register 0x0000_0000 SYS_IRCTIEN SYS_BA 0xF4 R W HIRC Trim Interrupt Enable Register 0x0000_0000 SYS_IRCTISTS SYS_BA 0xF8 R W HIRC Trim Interrupt Status Regist...

Page 192: ...SYS_BA 0x00 R Part Device Identification Number Register 0xXXXX_XXXX 1 1 Every part number has a unique default reset value 31 30 29 28 27 26 25 24 PDID 23 22 21 20 19 18 17 16 PDID 15 14 13 12 11 10...

Page 193: ...ly 0 No reset from CPU lockup happened 1 The Cortex M4 lockup happened and chip is reset Note Write 1 to clear this bit to 0 7 CPURF CPU Reset Flag The CPU reset flag is set by hardware if software wr...

Page 194: ...om watchdog timer or window watchdog timer 1 The watchdog timer or window watchdog timer had issued the reset signal to reset the system Note1 Write 1 to clear this bit to 0 Note2 Watchdog Timer regis...

Page 195: ...Controller Reset Write Protect M45xG M45xE Only Set this bit to 1 will generate a reset signal to the USB host controller User needs to set this bit to 0 to release from the reset state 0 USBH contro...

Page 196: ...t Reset Write Protect Setting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles The CHIPRST is same a...

Page 197: ...I2C1RST I2C0RST 7 6 5 4 3 2 1 0 ACMP01RST Reserved TMR3RST TMR2RST TMR1RST TMR0RST GPIORST Reserved Bits Description 31 29 Reserved Reserved 28 EADCRST EADC Controller Reset 0 EADC controller normal o...

Page 198: ...rmal operation 1 I2C1 controller reset 8 I2C0RST I2C0 Controller Reset 0 I2C0 controller normal operation 1 I2C0 controller reset 7 ACMP01RST Analog Comparator 0 1 Controller Reset 0 Analog Comparator...

Page 199: ...ster 2 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved PWM1RST PWM0RST 15 14 13 12 11 10 9 8 Reserved DACRST Reserved 7 6 5 4 3 2 1 0 Reserved SC0RST Bits Description 31...

Page 200: ...EN Bits Description 31 15 Reserved Reserved 14 12 LVRDGSEL LVR Output De glitch Time Select Write Protect 000 Without de glitch function 001 4 system clock HCLK 010 8 system clock HCLK 011 16 system c...

Page 201: ...h the voltage of BODVL setting 1 When Brown out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting this bit is s...

Page 202: ...Detector Enable Bit Write Protect The default value is set by flash controller user configuration register CBODEN CONFIG0 23 0 Brown out Detector function Disabled 1 Brown out Detector function Enabl...

Page 203: ...ain Buffer Enable Bit This bit is used to enable disable VBAT unity gain buffer function 0 VBAT unity gain buffer function Disabled default 1 VBAT unity gain buffer function Enabled Note After this bi...

Page 204: ...d 15 0 POROFF Power on Reset Enable Bit Write Protect When powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again Us...

Page 205: ...served 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved VREFCTL Bits Description 31 5 Reserved Reserved 4 0 VREFCTL VREF Control Bits Write Protect 00000 VREF is from external pin 00011 VREF is...

Page 206: ...EN 7 6 5 4 3 2 1 0 Reserved USBROLE Bits Description 31 9 Reserved Reserved 8 LDO33EN USB LDO33 Enable Bit Write Protect M45xG M45xE Only 0 USB LDO33 Disabled 1 USB LDO33 Enabled Note This bit is writ...

Page 207: ...0 31 30 29 28 27 26 25 24 PA7MFP PA6MFP 23 22 21 20 19 18 17 16 PA5MFP PA4MFP 15 14 13 12 11 10 9 8 PA3MFP PA2MFP 7 6 5 4 3 2 1 0 PA1MFP PA0MFP Bits Description 31 28 PA7MFP PA 7 Multi function Pin Se...

Page 208: ...29 28 27 26 25 24 PA15MFP PA14MFP 23 22 21 20 19 18 17 16 PA13MFP PA12MFP 15 14 13 12 11 10 9 8 PA11MFP PA10MFP 7 6 5 4 3 2 1 0 PA9MFP PA8MFP Bits Description 31 28 PA15MFP PA 15 Multi function Pin Se...

Page 209: ...0 31 30 29 28 27 26 25 24 PB7MFP PB6MFP 23 22 21 20 19 18 17 16 PB5MFP PB4MFP 15 14 13 12 11 10 9 8 PB3MFP PB2MFP 7 6 5 4 3 2 1 0 PB1MFP PB0MFP Bits Description 31 28 PB7MFP PB 7 Multi function Pin Se...

Page 210: ...29 28 27 26 25 24 PB15MFP PB14MFP 23 22 21 20 19 18 17 16 PB13MFP PB12MFP 15 14 13 12 11 10 9 8 PB11MFP PB10MFP 7 6 5 4 3 2 1 0 PB9MFP PB8MFP Bits Description 31 28 PB15MFP PB 15 Multi function Pin Se...

Page 211: ...0 31 30 29 28 27 26 25 24 PC7MFP PC6MFP 23 22 21 20 19 18 17 16 PC5MFP PC4MFP 15 14 13 12 11 10 9 8 PC3MFP PC2MFP 7 6 5 4 3 2 1 0 PC1MFP PC0MFP Bits Description 31 28 PC7MFP PC 7 Multi function Pin Se...

Page 212: ...29 28 27 26 25 24 PC15MFP PC14MFP 23 22 21 20 19 18 17 16 PC13MFP PC12MFP 15 14 13 12 11 10 9 8 PC11MFP PC10MFP 7 6 5 4 3 2 1 0 PC9MFP PC8MFP Bits Description 31 28 PC15MFP PC 15 Multi function Pin Se...

Page 213: ...0 31 30 29 28 27 26 25 24 PD7MFP PD6MFP 23 22 21 20 19 18 17 16 PD5MFP PD4MFP 15 14 13 12 11 10 9 8 PD3MFP PD2MFP 7 6 5 4 3 2 1 0 PD1MFP PD0MFP Bits Description 31 28 PD7MFP PD 7 Multi function Pin Se...

Page 214: ...29 28 27 26 25 24 PD15MFP PD14MFP 23 22 21 20 19 18 17 16 PD13MFP PD12MFP 15 14 13 12 11 10 9 8 PD11MFP PD10MFP 7 6 5 4 3 2 1 0 PD9MFP PD8MFP Bits Description 31 28 PD15MFP PD 15 Multi function Pin Se...

Page 215: ...0 31 30 29 28 27 26 25 24 PE7MFP PE6MFP 23 22 21 20 19 18 17 16 PE5MFP PE4MFP 15 14 13 12 11 10 9 8 PE3MFP PE2MFP 7 6 5 4 3 2 1 0 PE1MFP PE0MFP Bits Description 31 28 PE7MFP PE 7 Multi function Pin Se...

Page 216: ...0000 31 30 29 28 27 26 25 24 Reserved PE14_MFP 23 22 21 20 19 18 17 16 PE13MFP PE12MFP 15 14 13 12 11 10 9 8 PE11MFP PE10MFP 7 6 5 4 3 2 1 0 PE9MFP PE8MFP Bits Description 31 28 Reserved Reserved 27 2...

Page 217: ...0 31 30 29 28 27 26 25 24 PF7MFP PF6MFP 23 22 21 20 19 18 17 16 PF5MFP PF4MFP 15 14 13 12 11 10 9 8 PF3MFP PF2MFP 7 6 5 4 3 2 1 0 PF1MFP PF0MFP Bits Description 31 28 PF7MFP PF 7 Multi function Pin Se...

Page 218: ...S_SRAM_INTCTL SYS_BA 0xC0 R W System SRAM Interrupt Enable Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0...

Page 219: ...on Reset Value SYS_SRAM_STATUS SYS_BA 0xC4 R System SRAM Parity Error Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5...

Page 220: ...W Description Reset Value SYS_SRAM_ERRADDR SYS_BA 0xC8 R System SRAM Parity Check Error Address Register 0x0000_0000 31 30 29 28 27 26 25 24 ERRADDR 23 22 21 20 19 18 17 16 ERRADDR 15 14 13 12 11 10...

Page 221: ...able Bit Write Protect This bit enables BIST test for CAN RAM 0 system CAN BIST Disabled 1 system CAN BIST Enabled Note This bit is write protected Refer to the SYS_REGLCTL register 2 CRBIST CACHE BIS...

Page 222: ...ST Test Finish 0 USB SRAM BIST is active 1 USB SRAM BIST test finish 19 CANBEND CAN SRAM BIST Test Finish 0 CAN SRAM BIST is active 1 CAN SRAM BIST test finish 18 CRBEND CACHE SRAM BIST Test Finish 0...

Page 223: ...FERENCE MANUAL 1 System CACHE RAM BIST test fail 1 SRBISTEF1 2nd System SRAM BIST Fail Flag 0 2nd system SRAM BIST test pass 1 2nd system SRAM BIST test fail 0 SRBISTEF0 1st System SRAM BIST Fail Flag...

Page 224: ...eration will be disabled and FREQSEL will be cleared to 00 00 Trim retry count limitation is 64 loops 01 Trim retry count limitation is 128 loops 10 Trim retry count limitation is 256 loops 11 Trim re...

Page 225: ...HNICAL REFERENCE MANUAL 00 Disable HIRC auto trim function 01 Enable HIRC auto trim function and trim HIRC to 22 1184 MHz Others Reserved Note HIRC auto trim cannot work normally at power down mode Th...

Page 226: ...2 is set during auto trim operation an interrupt will be triggered to notify the clock frequency is inaccuracy 0 Disable CLKERRIF SYS_IRCTSTS 2 status to trigger an interrupt to CPU 1 Enable CLKERRIF...

Page 227: ...bit is set and CLKEIEN SYS_IRCTIEN 2 is high an interrupt will be triggered to notify the clock frequency is inaccuracy Write 1 to clear this to 0 0 Clock frequency is accuracy 1 Clock frequency is in...

Page 228: ...to enable register protection This register is written to disable enable register protection and read for the REGLCTL status Register Offset R W Description Reset Value SYS_REGLCTL SYS_BA 0x100 R W R...

Page 229: ...0 ISP Trigger Control register FMC_ISPSTS address 0x4000_C040 WDT_CTL address 0x4004_0000 FMC_FTCTL address 0x4000_5018 SYS_AHBMCTL address 0x40000400 CLK_PLLCTL address 0x40000240 PWM_CTL0 address 0x...

Page 230: ...0 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved INTACTEN Bits Description 31 1 Reserved Reserved 0 INTACTEN Highest AHB Bus Priori...

Page 231: ...value is UNKNOWN on reset Software should write to the register to clear it to zero before enabling the feature This ensures the timer will count from the SYST_LOAD value rather than an arbitrary val...

Page 232: ...time this register was read COUNTFLAG is set by a count transition from 1 to 0 COUNTFLAG is cleared on read or by a write to the Current Value register 15 3 Reserved Reserved 2 CLKSRC System Tick Clo...

Page 233: ...on Reset Value SYST_LOAD SCS_BA 0x14 R W SysTick Reload Value Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 RELOAD 15 14 13 12 11 10 9 8 RELOAD 7 6 5 4 3 2 1 0 RELOAD B...

Page 234: ...Reserved 23 22 21 20 19 18 17 16 CURRENT 15 14 13 12 11 10 9 8 CURRENT 7 6 5 4 3 2 1 0 CURRENT Bits Description 31 24 Reserved Reserved 23 0 CURRENT System Tick Current Value Current counter value Th...

Page 235: ...Power Sleep mode support The processor automatically stacks its state on exception entry and unstacks this state on exception exit with no instruction overhead This provides low latency exception han...

Page 236: ...w Watchdog Timer interrupt 26 10 EINT0 External interrupt from PA 0 PD 2 or PE 4 pins 27 11 EINT1 External interrupt from PB 0 PD 3 or PE 5 pins 28 12 EINT2 External interrupt from PC 0 pin 29 13 EINT...

Page 237: ...Timer 0 interrupt 49 33 TMR1_INT Timer 1 interrupt 50 34 TMR2_INT Timer 2 interrupt 51 35 TMR3_INT Timer 3 interrupt 52 36 UART0_INT UART0 interrupt 53 37 UART1_INT UART1 interrupt 54 38 I2C0_INT I2C0...

Page 238: ...rupt to become Pending however the interrupt will not activate If an interrupt is Active when it is disabled it remains in its Active state until cleared by reset or an exception return Clearing the e...

Page 239: ...nable Control Register 0x0000_0000 NVIC_ISPR1 NVIC_BA 0x100 R W IRQ0 IRQ63 Set Pending Control Register 0x0000_0000 NVIC_ISPR2 NVIC_BA 0x104 R W IRQ0 IRQ63 Set Pending Control Register 0x0000_0000 NVI...

Page 240: ...IRQ63 Set Enable Control Register 0x0000_0000 31 30 29 28 27 26 25 24 SETENA 23 22 21 20 19 18 17 16 SETENA 15 14 13 12 11 10 9 8 SETENA 7 6 5 4 3 2 1 0 SETENA Bits Description 31 0 SETENA Interrupt S...

Page 241: ...IRQ63 Set Enable Control Register 0x0000_0000 31 30 29 28 27 26 25 24 SETENA 23 22 21 20 19 18 17 16 SETENA 15 14 13 12 11 10 9 8 SETENA 7 6 5 4 3 2 1 0 SETENA Bits Description 31 0 SETENA Interrupt S...

Page 242: ...Q63 Clear Enable Control Register 0x0000_0000 31 30 29 28 27 26 25 24 CALENA 23 22 21 20 19 18 17 16 CALENA 15 14 13 12 11 10 9 8 CALENA 7 6 5 4 3 2 1 0 CALENA Bits Description 31 0 CALENA Interrupt C...

Page 243: ...Q63 Clear Enable Control Register 0x0000_0000 31 30 29 28 27 26 25 24 CALENA 23 22 21 20 19 18 17 16 CALENA 15 14 13 12 11 10 9 8 CALENA 7 6 5 4 3 2 1 0 CALENA Bits Description 31 0 CALENA Interrupt C...

Page 244: ...Register 0x0000_0000 31 30 29 28 27 26 25 24 SETPEND 23 22 21 20 19 18 17 16 SETPEND 15 14 13 12 11 10 9 8 SETPEND 7 6 5 4 3 2 1 0 SETPEND Bits Description 31 0 SETPEND Interrupt Set pending The NVIC...

Page 245: ...Register 0x0000_0000 31 30 29 28 27 26 25 24 SETPEND 23 22 21 20 19 18 17 16 SETPEND 15 14 13 12 11 10 9 8 SETPEND 7 6 5 4 3 2 1 0 SETPEND Bits Description 31 0 SETPEND Interrupt Set pending The NVIC...

Page 246: ...Register 0x0000_0000 31 30 29 28 27 26 25 24 CALPEND 23 22 21 20 19 18 17 16 CALPEND 15 14 13 12 11 10 9 8 CALPEND 7 6 5 4 3 2 1 0 CALPEND Bits Description 31 0 CALPEND Interrupt Clear pending The NV...

Page 247: ...Register 0x0000_0000 31 30 29 28 27 26 25 24 CALPEND 23 22 21 20 19 18 17 16 CALPEND 15 14 13 12 11 10 9 8 CALPEND 7 6 5 4 3 2 1 0 CALPEND Bits Description 31 0 CALPEND Interrupt Clear pending The NV...

Page 248: ...Value NVIC_IABR1 NVIC_BA 0x200 R W IRQ0 IRQ63 Active Bit Register 0x0000_0000 31 30 29 28 27 26 25 24 ACTIVE 23 22 21 20 19 18 17 16 ACTIVE 15 14 13 12 11 10 9 8 ACTIVE 7 6 5 4 3 2 1 0 ACTIVE Bits De...

Page 249: ...Value NVIC_IABR2 NVIC_BA 0x204 R W IRQ0 IRQ63 Active Bit Register 0x0000_0000 31 30 29 28 27 26 25 24 ACTIVE 23 22 21 20 19 18 17 16 ACTIVE 15 14 13 12 11 10 9 8 ACTIVE 7 6 5 4 3 2 1 0 ACTIVE Bits De...

Page 250: ...n_1 Reserved 7 6 5 4 3 2 1 0 PRI_4n_0 Reserved Bits Description 31 28 PRI_4n_3 Priority of IRQ_4n 3 0 denotes the highest priority and 15 denotes the lowest priority 27 24 Reserved Reserved 23 20 PRI_...

Page 251: ...n_1 Reserved 7 6 5 4 3 2 1 0 PRI_4n_0 Reserved Bits Description 31 28 PRI_4n_3 Priority of IRQ_4n 3 0 denotes the highest priority and 15 denotes the lowest priority 27 24 Reserved Reserved 23 20 PRI_...

Page 252: ...29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved INTID 7 6 5 4 3 2 1 0 INTID Bits Description 31 9 Reserved Reserved 8 0 INTID Interrupt ID Write to the STIR...

Page 253: ...l Registers 6 2 10 4 R read only W write only R W both read and write Register Offset R W Description Reset Value NMI Base Address NMI_BA 0x4000_0300 NMIEN NMI_BA 0x00 R W NMI Source Interrupt Enable...

Page 254: ...nal Interrupt From PF 0 Pin NMI Source Enable Write Protect 0 External interrupt from PF 0 pin NMI source Disabled 1 External interrupt from PF 0 pin NMI source Enabled Note This bit is write protecte...

Page 255: ...ed Note This bit is write protected Refer to the SYS_REGLCTL register 5 Reserved Reserved 4 CLKFAIL Clock Fail Detected NMI Source Enable Write Protect 0 Clock fail detected interrupt NMI source Disab...

Page 256: ...errupt is deasserted 1 External Interrupt from PF 0 interrupt is asserted 12 EINT4 External Interrupt From PE 0 Pin Interrupt Flag Read Only 0 External Interrupt from PE 0 interrupt is deasserted 1 Ex...

Page 257: ...0 Clock fail detected interrupt is deasserted 1 Clock fail detected interrupt is asserted 3 SRAM_PERR SRAM ParityCheck Error Interrupt Flag Read Only 0 SRAM parity check error interrupt is deasserted...

Page 258: ...ference Manual and ARM v6 M Architecture Reference Manual R read only W write only R W both read and write Register Offset R W Description Reset Value SCR Base Address SCS_BA 0xE000_E000 ICSR SCS_BA 0...

Page 259: ...is the highest priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit Entering the handler then clears this bit to 0 This means a re...

Page 260: ...terrupt Pending Flag Excluding NMI and Faults Read Only 0 Interrupt not pending 1 Interrupt pending 21 18 Reserved Reserved 17 12 VECTPENDING Number of the Highest Pended Exception Indicate the Except...

Page 261: ...nt accidental write to this register from resetting the system or clearing of the exception status 15 ENDIANNESS Data Endianness 0 Little endian 1 Big endian 14 11 Reserved Reserved 10 8 PRIGROUP Inte...

Page 262: ...bpriority Bits Number Of Group Priorities Subpriorities 0b000 bxxxxxxx y 7 1 0 128 2 0b001 bxxxxxx yy 7 2 1 0 64 4 0b010 bxxxxx yyy 7 3 2 0 32 8 0b011 bxxxx yyyy 7 4 3 0 16 16 0b100 bxxx yyyyy 7 5 4 0...

Page 263: ...up the processor When an event or interrupt enters pending state the event signal wakes up the processor from WFE If the processor is not waiting for an event the event is registered and affects the n...

Page 264: ...1 SCS_BA 0xD18 R W System Handler Priority Register 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 PRI_6 15 14 13 12 11 10 9 8 PRI_5 7 6 5 4 3 2 1 0 PRI_4 Bits Description 31 2...

Page 265: ...Value SHPR2 SCS_BA 0xD1C R W System Handler Priority Register 2 0x0000_0000 31 30 29 28 27 26 25 24 PRI_11 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Rese...

Page 266: ...00 31 30 29 28 27 26 25 24 PRI_15 Reserved 23 22 21 20 19 18 17 16 PRI_14 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Description 31 30 PRI_15 Priority of System Handler 15 S...

Page 267: ...clock divider The chip will not enter Power down mode until CPU sets the Power down enable bit PDEN CLK_PWRCTL 7 and Cortex M4 core executes the WFI instruction After that chip enters Power down mode...

Page 268: ...32 768 kHz CLK_CLKSEL1 25 24 111 22 1184 MHz 101 10 kHz 011 T0 T1 HCLK 4 24 MHz 22 1184 MHz 32 768 kHz CLK_CLKSEL1 29 28 11 10 01 00 USB 1 USBDIV 1 PLLFOUT SPI2 PCLK0 4 24 MHz 22 1184 MHz PLLFOUT CLK...

Page 269: ...lected from external 4 20 MHz external high speed crystal HXT or 22 1184 MHz internal high speed oscillator HIRC 22 1184 MHz internal high speed RC oscillator HIRC 10 kHz internal low speed RC oscilla...

Page 270: ...ce and they have individual enable and interrupt control When HXT detector is enabled the HIRC clock is enabled automatically When LXT detector is enabled the LIRC clock is enabled automatically When...

Page 271: ...ock STCLK has 5 clock sources The clock source switch depends on the setting of the register STCLKSEL CLK_CLKSEL0 5 3 The block diagram is shown in the Figure 6 3 5 111 011 010 001 HXT LXT HXT HCLK ST...

Page 272: ...he 16 shift register outputs selected by a sixteen to one multiplexer is reflected to CLKO function pin Therefore there are 16 options of power of 2 divided clocks with the frequency from Fin 2 1 to F...

Page 273: ...to 1 MUX 1 2 1 22 1 23 1 215 1 216 FREQSEL CLK_CLKOCTL 3 0 CLKO 16 chained divide by 2 counter CLKOEN CLK_CLKOCTL 4 Enable divide by 2 counter 0 1 DIV1EN CLK_CLKOCTL 5 CLKO_CLK 0 1 CLK1HZEN CLK_CLKOCT...

Page 274: ...rce Select Control Register 1 0xB377_770F CLK_CLKSEL2 CLK_BA 0x18 R W Clock Source Select Control Register 2 0x0000_00AB CLK_CLKSEL3 CLK_BA 0x1C R W Clock Source Select Control Register 3 0x0000_0003...

Page 275: ...frequency is higher than 16 MHz Note This bit is write protected Refer to the SYS_REGLCTL register 9 Reserved Reserved 8 PDWTCPU this Bit Control the Power down Entry Condition Write Protect 0 Chip en...

Page 276: ...lock cycles when chip works at 4 20 MHz external high speed crystal oscillator HXT and 256 clock cycles when chip works at 22 1184 MHz internal high speed RC oscillator HIRC 0 Clock cycles delay Disab...

Page 277: ...mode 1 1 1 YES Most clocks are disabled except LIRC LXT and only RTC WDT Timer peripheral clocks still enable if their clock sources are selected as LIRC LXT Table 6 9 Power down Mode Control Table Wh...

Page 278: ...Clock Enable Bit in IDLE Mode 0 FMC peripheral clock Disabled when chip operating at IDLE mode 1 FMC peripheral clock Enabled when chip operating at IDLE mode 14 8 Reserved Reserved 7 CRCCKEN CRC Gen...

Page 279: ...0CKEN 7 6 5 4 3 2 1 0 ACMP01CKEN CLKOCKEN TMR3CKEN TMR2CKEN TMR1CKEN TMR0CKEN RTCCKEN WDTCKEN Bits Description 31 29 Reserved Reserved 28 EADCCKEN Enhanced Analog digital converter EADC Clock Enable B...

Page 280: ...1CKEN Analog Comparator 0 1 Clock Enable Bit 0 Analog comparator 0 1 clock Disabled 1 Analog comparator 0 1 clock Enabled 6 CLKOCKEN CLKO Clock Enable Bit 0 CLKO clock Disabled 1 CLKO clock Enabled 5...

Page 281: ...1 SERIES TECHNICAL REFERENCE MANUAL 1 RTC APB clock Enabled 0 WDTCKEN Watchdog Timer Clock Enable Bit Write Protect 0 Watchdog timer clock Disabled 1 Watchdog timer clock Enabled Note This bit is writ...

Page 282: ...00 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved PWM1CKEN PWM0CKEN 15 14 13 12 11 10 9 8 Reserved DACCKEN Reserved 7 6 5 4 3 2 1 0 Reserved SC0CKEN Bits Description 31 18 Reserved...

Page 283: ...rce from HCLK 2 Note This bit is write protected Refer to the SYS_REGLCTL register 5 3 STCLKSEL Cortex M4 SysTick Clock Source Selection Write Protect If SYST_CTRL 2 0 SysTick uses listed clock source...

Page 284: ...4 2018 Page 284 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL 011 Clock source from LIRC 111 Clock source from HIRC Other Reserved Note This bit is write protected Refer to the SYS_REGLCTL...

Page 285: ...00 Clock source from 4 20 MHz external high speed crystal oscillator HXT 01 Clock source from 32 768 kHz external low speed crystal oscillator LXT 10 Clock source from HCLK 11 Clock source from 22 11...

Page 286: ...lock source from external clock T1 pin 101 Clock source from 10 kHz internal low speed RC oscillator LIRC 111 Clock source from 22 1184 MHz internal high speed RC oscillator HIRC Others Reserved 11 Re...

Page 287: ...rom PLL 10 Clock source from PCLK0 11 Clock source from 22 1184 MHz internal high speed RC oscillator HIRC 5 4 SPI1SEL SPI1 Clock Source Selection 00 Clock source from 4 20 MHz external high speed cry...

Page 288: ...ved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved RTCSEL 7 6 5 4 3 2 1 0 Reserved SC0SEL Bits Description 31 9 Reserved Reserved 8 RTCSEL RTC Clock Source Selection 0 Clock source fr...

Page 289: ...6 5 4 3 2 1 0 USBDIV HCLKDIV Bits Description 31 24 Reserved Reserved 23 16 EADCDIV EADC Clock Divide Number From EADC Clock Source EADC clock frequency EADC clock source frequency EADCDIV 1 15 12 Res...

Page 290: ...Reset Value CLK_CLKDIV 1 CLK_BA 0x24 R W Clock Divider Number Register 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 SC...

Page 291: ...nter Selection Write Protect 0 PLL stable time is 6144 PLL source clock suitable for source clock is equal to or less than 12 MHz 1 PLL stable time is 12288 PLL source clock suitable for source clock...

Page 292: ...er to the formulas below the table Note This bit is write protected Refer to the SYS_REGLCTL register 8 0 FBDIV PLL Feedback Divider Control Write Protect Refer to the formulas below the table Note Th...

Page 293: ...e Write 1 to clear the bit to 0 6 5 Reserved Reserved 4 HIRCSTB HIRC Clock Source Stable Flag Read Only 0 22 1184 MHz internal high speed RC oscillator HIRC clock is not stable or disabled 1 22 1184 M...

Page 294: ...Clock Output 1Hz Enable Bit 0 1 Hz clock output for 32 768 kHz frequency compensation Disabled 1 1 Hz clock output for 32 768 kHz frequency compensation Enabled 5 DIV1EN Clock Output Divide One Enable...

Page 295: ...r HXT clock frequency monitor Disabled 1 4 20 MHz external high speed crystal oscillator HXT clock frequency monitor Enabled 15 14 Reserved Reserved 13 LXTFIEN LXT Clock Fail Interrupt Enable Bit 0 32...

Page 296: ...equency Monitor Interrupt Flag 0 4 20 MHz external high speed crystal oscillator HXT clock is normal 1 4 20 MHz external high speed crystal oscillator HXT clock frequency is abnormal Note Write 1 to c...

Page 297: ...Upper Boundary Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved UPERBD 7 6 5 4 3 2 1 0 UPERBD Bits Description 31 10 Reserved Reser...

Page 298: ...Lower Boundary Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved LOWERBD 7 6 5 4 3 2 1 0 LOWERBD Bits Description 31 10 Reserved Res...

Page 299: ...plication Programming IAP function user switches the code executing without the chip reset after the embedded flash updated 6 4 2 Features Supports 40 72 128 256 KB application ROM APROM Supports 4 KB...

Page 300: ...bedded flash memory The block diagram of flash memory controller is shown as follows Flash Operation Controller Flash Initialization Controller AHB Slave Interface Loader ROM LDROM 4KB Embedded Flash...

Page 301: ...M451 May 4 2018 Page 301 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL...

Page 302: ...ter Description section Flash Initialization Controller When chip is powered on or active from reset the flash initialization controller will start to access flash automatically and check the flash st...

Page 303: ...OM and Data Flash LDROM is designed for a loader to implement In System Programming ISP function by user LDROM is a 4KB embedded flash memory the flash address range is from 0x0010_0000 to 0x0010_0FFF...

Page 304: ...oltage level and Data Flash base address It works like a fuse for power on setting It is loaded from flash memory to its corresponding control registers during chip power on User can set these bits ac...

Page 305: ...PWRCTL 3 if CWDTPDEN is 1 Please refer to bit field description of CWDTPDEN 111 WDT hardware enable function is inactive Others WDT hardware enable function is active WDT clock is always on 30 CWDTPDE...

Page 306: ...SPCTL 1 is only be used to control boot switching when CBS 0 1 VECMAP FMC_ISPSTS 23 9 is only be used to remap 0x0 0x1ff when CBS 0 0 5 Reserved Reserved 4 3 CWDTEN 1 0 Watchdog Timer Hardware Enable...

Page 307: ...18 17 16 Reserved DFBA 15 14 13 12 11 10 9 8 DFBA 7 6 5 4 3 2 1 0 DFBA Bits Descriptions 31 20 Reserved Reserved 19 0 DFBA Data Flash Base Address This register works only when DFEN CONFIG0 0 set to...

Page 308: ..._0000 0x0010_0000 Loader ROM LDROM 4KB 0x0010_0FFF APROM 40KB Device 72KB 0x0003_FFFF 256KB 0x0001_FFFF ApplicationROM APROM ApplicationROM APROM Loader ROM LDROM 4KB Reserved Reserved Reserved APROM...

Page 309: ...APROM region for Cortex M4 instruction access The address from 0x0000_0000 to 0x0000_01FF is called system memory vector APROM and LDROM can map to the system memory vector for CPU start up There are...

Page 310: ...vector for Cortex M4 instruction or data access 0x0000_0000 ApplicationROM APROM 0x0000_01FF 0x0000_0200 System Memory Vector 0x0000_01FF 0x0000_0000 APROM 512B Figure 6 4 6 APROM with IAP Mode In sys...

Page 311: ...cannot run to access LDROM The Data Flash is shared with APROM and the Data Flash base address is defined by CONFIG1 The content of CONFIG1 is loaded into DFBA Data Flash Base Address Register at the...

Page 312: ...eries provides In Application Programming IAP function for user to switch the code executing between APROM and LDROM User can enable the IAP function by booting chip and setting the chip boot selectio...

Page 313: ...A FMC_MPDAT0 LSB Programming Data FMC_MPDAT1 MSB Programming Data FMC_MPDAT2 FMC_MPDAT3 N A FLASH Multi Word Program 0x27 Valid address of flash memory organization FMC_ISPDAT N A FMC_MPDAT0 1 st Prog...

Page 314: ...re The FMC controller provides embedded flash memory read erase and program operation Several control bits of FMC control register are write protected thus it is necessary to unlock before setting Aft...

Page 315: ...SPFF FMC_ISPSTS 6 bit is kept as 1 Therefore it is recommended to check the ISPFF FMC_ISPSTS 6 bit and clear it after each ISP operation if it is set to 1 When the ISPGO FMC_ISPTRG 0 bit is set CPU wi...

Page 316: ...Data3 Register N A N A FMC_MPSTS ISP Multi Program status N A N A FMC_MPADDR ISP Multi Program Address N A N A Table 6 4 3 FMC control registers for Flash Programming 64 bit Programming The NuMicro M4...

Page 317: ...rite FMC_ISPCMD Write FMC_ISPDAT Add ISB instruction Check ISPGO 0 NO YES Start Stop Figure 6 4 10 ISP 32 bit Programming Procedure Enable ISPEN Set ISPGO 1 End of ISP Operation Check ISPFF 1 YES End...

Page 318: ...hold time needed for one time operation 32 bit Programming 64 bit Programming Multi Word Programming SETUP TIME fix 4 bytes programming HOLD TIME SETUP TIME fix 8 bytes programming HOLD TIME SETUP TI...

Page 319: ...th word is FMC_MPDAT3 If the starting ISP address FMC_ISPADDR 3 is 1 the 1 st data word should put on FMC_MPDAT2 and 2 nd word is FMC_MPDAT3 3 rd word is FMC_MPDAT0 and 4 th word is FMC_MPDAT1 The max...

Page 320: ...T3 Y N Enable ISPEN Set ISPGO 1 End of ISP Operation Y Programming Finish Read FMC_MPSTS MPBUSY 0 N Y Write FMC_MPDAT0 Write FMC_MPDAT1 Read FMC_MPSTS N Y MPBUSY 0 N Y Write FMC_MPDAT2 Write FMC_MPDAT...

Page 321: ...he comparison result is saved in PGFF FMC_ISPSTS 5 The PGFF is set to 1 if output data is not the same as the input programming data The flag is kept until clear by software or a new erase operation T...

Page 322: ...it programming and 64 bit programming operation but multi word programming operation is not suitable due to the embedded flash HV High Voltage of continue programming Checksum Calculation 6 4 4 7 The...

Page 323: ...uld be 2 KB and the starting address includes APROM and LDROM In step 2 the FMC_ISPADDR should be kept as the same as step 1 In step 3 the checksum is read from FMC_ISPDAT If the checksum is 0x0000_00...

Page 324: ...M451 May 4 2018 Page 324 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL Figure 6 4 18 Checksum Calculation Flow...

Page 325: ...er 0x0000_0000 FMC_ISPTRG FMC_BA 0x10 R W ISP Trigger Control Register 0x0000_0000 FMC_DFBA FMC_BA 0x14 R Data Flash Base Address 0xXXXX_XXXX FMC_FTCTL FMC_BA 0x18 R W Flash Access Time Control Regist...

Page 326: ...UEN is set to 0 3 CONFIG is erased programmed if CFGUEN is set to 0 4 Page Erase command at LOCK mode with ICE connection 5 Erase or Program command at brown out detected 6 Destination address is ille...

Page 327: ...chip booted from This bit is initiated with the inversed value of CBS 1 CONFIG0 7 after any reset is happened except CPU reset CPU is 1 or system reset SYS is happened 0 Booting from APROM 1 Booting...

Page 328: ...23 22 21 20 19 18 17 16 ISPADDR 15 14 13 12 11 10 9 8 ISPADDR 7 6 5 4 3 2 1 0 ISPADDR Bits Description 31 0 ISPADDR ISP Address The NuMicro M451 series is equipped with embedded flash ISPADDR 1 0 must...

Page 329: ...0 9 8 ISPDAT 7 6 5 4 3 2 1 0 ISPDAT Bits Description 31 0 ISPDAT ISP Data Write data to this register before ISP program operation Read data from this register after ISP read operation For Run Checksu...

Page 330: ...7 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CMD Bits Description 31 7 Reserved Reserved 6 0 CMD ISP CMD ISP command table is shown below 0x00 FLASH 32 bit Read 0x40 FLASH 64...

Page 331: ...29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved ISPGO Bits Description 31 1 Reserved Reserved 0 ISPGO ISP Start Trigger Write Protec...

Page 332: ...lash Base Address 0xXXXX_XXXX 31 30 29 28 27 26 25 24 DFBA 23 22 21 20 19 18 17 16 DFBA 15 14 13 12 11 10 9 8 DFBA 7 6 5 4 3 2 1 0 DFBA Bits Description 31 0 DFBA Data Flash Base Address This register...

Page 333: ...20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved FOM Reserved Bits Description 31 7 Reserved Reserved 6 4 FOM Frequency Optimization Mode Write Protect The NuMicro M451...

Page 334: ...needs to be cleared by writing 1 to FMC_ISPCTL 6 or FMC_ISPSTS 6 This bit is set by hardware when a triggered ISP meets any of the following conditions 1 APROM writes to itself if APUEN is set to 0 2...

Page 335: ...ept CPU reset CPU is 1 or system reset SYS is happened 00 LDROM with IAP mode 01 LDROM without IAP mode 10 APROM with IAP mode 11 APROM without IAP mode 0 ISPBUSY ISP Busy Flag Read Only Write 1 to st...

Page 336: ...AT0 FMC_BA 0x80 R W ISP Data0 Register 0x0000_0000 31 30 29 28 27 26 25 24 ISPDAT0 23 22 21 20 19 18 17 16 ISPDAT0 15 14 13 12 11 10 9 8 ISPDAT0 7 6 5 4 3 2 1 0 ISPDAT0 Bits Description 31 0 ISPDAT0 I...

Page 337: ...fset R W Description Reset Value FMC_MPDAT1 FMC_BA 0x84 R W ISP Data1 Register 0x0000_0000 31 30 29 28 27 26 25 24 ISPDAT1 23 22 21 20 19 18 17 16 ISPDAT1 15 14 13 12 11 10 9 8 ISPDAT1 7 6 5 4 3 2 1 0...

Page 338: ...r Offset R W Description Reset Value FMC_MPDAT2 FMC_BA 0x88 R W ISP Data2 Register 0x0000_0000 31 30 29 28 27 26 25 24 ISPDAT2 23 22 21 20 19 18 17 16 ISPDAT2 15 14 13 12 11 10 9 8 ISPDAT2 7 6 5 4 3 2...

Page 339: ...Offset R W Description Reset Value FMC_MPDAT3 FMC_BA 0x8C R W ISP Data3 Register 0x0000_0000 31 30 29 28 27 26 25 24 ISPDAT3 23 22 21 20 19 18 17 16 ISPDAT3 15 14 13 12 11 10 9 8 ISPDAT3 7 6 5 4 3 2...

Page 340: ...ram to flash complete 6 D2 ISP DATA 2 Flag Read Only This bit is set when FMC_MPDAT2 is written and auto clear to 0 when the FMC_MPDAT2 data is programmed to flash complete 0 FMC_MPDAT2 register is em...

Page 341: ...ommand at LOCK mode with ICE connection 5 Erase or Program command at brown out detected 6 Destination address is illegal such as over an available range 7 Invalid ISP commands 1 PPGO ISP Multi progra...

Page 342: ..._BA 0xC4 R ISP Multi Program Address Register 0x0000_0000 31 30 29 28 27 26 25 24 MPADDR 23 22 21 20 19 18 17 16 MPADDR 15 14 13 12 11 10 9 8 MPADDR 7 6 5 4 3 2 1 0 MPADDR Bits Description 31 0 MPADDR...

Page 343: ...t 6 5 2 Features The External Bus Interface EBI has the following functions Supports address bus and data bus multiplex mode to save the address pins Supports two chip selects with polarity control Su...

Page 344: ...D_MFPL SYS_GPD_MFPH and SYS_GPE_MFPL Multiple Function Registers The EBI Controller clock are enabled in EBICKEN CLK_AHBCLK 3 6 5 5 Functional Description EBI Area and Address Hit 6 5 5 1 The EBI mapp...

Page 345: ...d the output of the latch device is connected to the address of external device For 16 bit device the EBI_AD 15 0 shared by address and 16 bit data EBI_ADR 18 16 is dedicated for address and could be...

Page 346: ...Q EBI_AD 7 0 EBI_AD 15 8 Addr 15 8 EBI_ADR 19 16 Addr 19 16 Figure 6 5 3 Connection of 8 bit EBI Data Width with 8 bit Device When system access data width is larger than EBI data width EBI controlle...

Page 347: ...EBI_nWR asserts to high after keeps access time tACC for reading output stable or writing finish After that EBI signals keep for data access hold time tAHD and chip select asserts to high address is r...

Page 348: ...ress output 18 16 Note The EBI_MCLK is HCLK 2 MCLKDIV EBI_CTLx 10 8 1 Figure 6 5 4 Timing Control Waveform for 16 bit Data Width Figure 6 5 4 shows an example of setting 16 bit data width In this exam...

Page 349: ...15 8 EBI_AD 15 8 Address output 15 8 EBI_ADR 19 16 Address output 19 16 EBI_ADR 19 16 Address output 19 16 Note The EBI_MCLK is HCLK 2 MCLKDIV EBI_CTLx 10 8 1 Figure 6 5 5 Timing Control Waveform for...

Page 350: ...8 1 Figure 6 5 6 Timing Control Waveform for Insert Idle Cycle There are two conditions that EBI can insert idle cycle by timing control 1 After write access 2 After read access and before next read...

Page 351: ...alue EBI Base Address EBI_BA 0x4001_0000 EBI_CTL0 EBI_BA 0x00 R W External Bus Interface Bank0 Control Register 0x0000_0000 EBI_TCTL0 EBI_BA 0x04 R W External Bus Interface Bank0 Timing Control Regist...

Page 352: ...CSPOLINV DW16 EN Bits Description 31 25 Reserved Reserved 24 WBUFEN EBI Write Buffer Enable Bit 0 EBI write buffer Disabled 1 EBI write buffer Enabled Note This bit only available in EBI_CTL0 registe...

Page 353: ...CS 0 Chip select pin EBI_nCS is active low 1 Chip select pin EBI_nCS is active high 1 DW16 EBI Data Width 16 bit Select This bit defines if the EBI data width is 8 bit or 16 bit 0 EBI data width is 8...

Page 354: ...ion is finish and next action is going to read R2R idle cycle is inserted and EBI_nCS return to idle state 23 WAHDOFF Access Hold Time Disable Control When Write 0 The Data Access Hold Time tAHD durin...

Page 355: ...M451 May 4 2018 Page 355 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL 2 0 Reserved Reserved...

Page 356: ...CONFIG0 10 Each I O pin has a very weakly individual pull up resistor which is about 110 k 300 k for VDD is from 5 0 V to 2 5 V 6 6 2 Features Four I O modes Quasi bidirectional mode Push Pull Output...

Page 357: ...rol Register Control Registers Interrupt Wake up Event Detector PB 15 0 PC 15 0 PD 15 0 PE 14 0 PF 7 0 GPIO_INT Figure 6 6 1 GPIO Controller Block Diagram Note The PB 9 PB 10 PC 9 PC 14 PC 15 PD 10 PD...

Page 358: ...the corresponding DOUT Px_DOUT n is driven on the pin Port Pin Port Pin N N P P VDD VDD Port Latch Data Port Latch Data Input Data Input Data Figure 6 6 2 Push Pull Output Open drain Mode 6 6 5 3 Set...

Page 359: ...or Note that the source current capability in quasi bidirectional mode is only about 200 uA to 30 uA for VDD is form 5 0 V to 2 5 V Port Pin Port Pin N N P P VDD VDD Port Latch Data Port Latch Data In...

Page 360: ..._BA 0x028 R W PA High Slew Rate Control Register 0x0000_0000 PB_MODE GPIO_BA 0x040 R W PB I O Mode Control 0xXXXX_XXXX PB_DINOFF GPIO_BA 0x044 R W PB Digital Input Path Disable Control 0x0000_0000 PB_...

Page 361: ...nable Control Register 0x0000_0000 PD_INTSRC GPIO_BA 0x0E0 R W PD Interrupt Source Flag 0x0000_XXXX PD_SMTEN GPIO_BA 0x0E4 R W PD Input Schmitt Trigger Enable Register 0x0000_0000 PD_SLEWCTL GPIO_BA 0...

Page 362: ...put Schmitt Trigger Enable Register 0x0000_0000 PF_SLEWCTL GPIO_BA 0x168 R W PF High Slew Rate Control Register 0x0000_0000 GPIO_DBCTL GPIO_BA 0x440 R W Interrupt De bounce Control Register 0x0000_002...

Page 363: ...10 MODE9 MODE8 15 14 13 12 11 10 9 8 MODE7 MODE6 MODE5 MODE4 7 6 5 4 3 2 1 0 MODE3 MODE2 MODE1 MODE0 Bits Description 2n 1 2n n 0 1 15 MODEn Port A f I O Pin N Mode Control Determine each I O mode of...

Page 364: ...DINOFF GPIO_BA 0x144 R W PF Digital Input Path Disable Control 0x0000_0000 31 30 29 28 27 26 25 24 DINOFF 23 22 21 20 19 18 17 16 DINOFF 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits De...

Page 365: ...27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 DOUT 7 6 5 4 3 2 1 0 DOUT Bits Description 31 16 Reserved Reserved n n 0 1 15 DOUT Port A f Pin N Output Value Each of these...

Page 366: ...20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 DATMSK 7 6 5 4 3 2 1 0 DATMSK Bits Description 31 8 Reserved Reserved n n 0 1 15 DATMSK Port A f Pin N Data Output Write Mask These bits are used to prote...

Page 367: ...XX PF_PIN GPIO_BA 0x150 R PF Pin Value 0x0000_00XX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 PIN 7 6 5 4 3 2 1 0 PIN Bits Description 31 16 Reserved Reser...

Page 368: ...7 6 5 4 3 2 1 0 DBEN Bits Description 31 16 Reserved Reserved n n 0 1 15 DBEN Port A f Pin N Input Signal De bounce Enable Bit The DBEN n bit is used to enable the de bounce function for each correspo...

Page 369: ...n 0 1 15 TYPE Port A f Pin N Edge or Level Detection Interrupt Trigger Type Control TYPE Px_INTTYPE n bit is used to control the triggered interrupt is by level trigger or by edge trigger If the inter...

Page 370: ...ng input Px n pin Set bit to 1 also enable the pin wake up function When setting the RHIEN Px_INTEN n 16 bit to 1 If the interrupt is level trigger TYPE Px_INTTYPE n bit is set to 1 the input Px n pin...

Page 371: ...Px n pin will generate the interrupt while this pin state changed from high to low 0 Px n level low or high to low interrupt Disabled 1 Px n level low or high to low interrupt Enabled Note1 Max n 15...

Page 372: ...BA 0x120 R W PE Interrupt Source Flag 0x0000_XXXX PF_INTSRC GPIO_BA 0x160 R W PF Interrupt Source Flag 0x0000_00XX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9...

Page 373: ...nable Register 0x0000_0000 PE_SMTEN GPIO_BA 0x124 R W PE Input Schmitt Trigger Enable Register 0x0000_0000 PF_SMTEN GPIO_BA 0x164 R W PF Input Schmitt Trigger Enable Register 0x0000_0000 31 30 29 28 2...

Page 374: ...ew Rate Control Register 0x0000_0000 PE_SLEWCTL GPIO_BA 0x128 R W PE High Slew Rate Control Register 0x0000_0000 PF_SLEWCTL GPIO_BA 0x168 R W PF High Slew Rate Control Register 0x0000_0000 31 30 29 28...

Page 375: ...gh Drive Strength Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved HDRVEN 13 8 7 6 5 4 3 2 1 0 Reserved Bits Description 31...

Page 376: ...er Clock Source Selection 0 De bounce counter clock source is the HCLK 1 De bounce counter clock source is the 10 kHz internal low speed RC oscillator LIRC 3 0 DBCLKSEL De bounce Sampling Cycle Select...

Page 377: ..._PDIO n 0 1 7 GPIO_BA 0x940 0x04 n R W GPIO PF n Pin Data Input Output Register 0x0000_000X 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2...

Page 378: ...iority fixed priority or round robin priority Supports transfer data width of 8 16 and 32 bits Supports source and destination address increment size can be byte half word word or no increment Support...

Page 379: ...urce address transfer destination address transfer count burst size transfer type and operation mode Figure 6 7 2 shows the diagram of descriptor table DSCT data structure Descriptor Table DSCT11 DSCT...

Page 380: ...e This mode can be used to transfer data between memory and memory or peripherals and memory PDMA controller operation mode can be set from OPMODE PDMA_DSCTn_CTL 1 0 n denotes PDMA channel default set...

Page 381: ...peration transfer Finishing each task will generate an interrupt to CPU if corresponding PDMA interrupt bit is enabled and TBINTDIS PDMA_DSCTn_CTL 7 bit is 0 when finishing task and TBINTDIS bit is 0...

Page 382: ...Mode as shown in Figure 6 7 5 When loading the information is finished it will go to transfer state and start transfer by this information automatically However if the next PDMA information is also in...

Page 383: ...Figure 6 7 6 shows an example about single and burst transfer type in basic mode In this example channel 1 uses single transfer type and TXCNT PDMA_DSCTn_CTL 29 16 128 Channel 0 uses burst transfer t...

Page 384: ...e channel has been selected to the peripheral the channel s corresponding time out counter will start count down where counter is based on 10KHz clock If time out counter counts to zero the PDMA contr...

Page 385: ...A 0x400 R W PDMA Channel Control Register 0x0000_0000 PDMA_STOP PDMA_BA 0x404 W PDMA Transfer Stop Control Register 0x0000_0000 PDMA_SWREQ PDMA_BA 0x408 W PDMA Software Request Register 0x0000_0000 PD...

Page 386: ...Time out Counter Ch5 and Ch4 Register M45xD M45xC Only 0xFFFF_FFFF PDMA_TOC6_7 PDMA_BA 0x44C R W PDMA Time out Counter Ch7 and Ch6 Register M45xD M45xC Only 0xFFFF_FFFF PDMA_REQSEL0_3 PDMA_BA 0x480 R...

Page 387: ...PDMA finish each transfer data this field will be decrease immediately 15 14 Reserved Reserved 13 12 TXWIDTH Transfer Width Selection This field is used for transfer width 00 One byte 8 bit is transf...

Page 388: ...burst transfer type 3 Reserved Reserved 2 TXTYPE Transfer Type 0 Burst transfer type 1 Single transfer type 1 0 OPMODE PDMA Operation Mode Selection 00 Idle state Channel is stopped or this table is c...

Page 389: ...alue PDMA_DSCTn_SA n 0 11 DSCT_SA_BA 0x10 n R W Source Address Register of PDMA Channel n M45xD M45xC Only Support Channel 0 7 0xXXXX_XXXX 31 30 29 28 27 26 25 24 SA 23 22 21 20 19 18 17 16 SA 15 14 1...

Page 390: ...A_DSCTn_DA n 0 11 DSCT_DA_BA 0x10 n R W Destination Address Register of PDMA Channel n M45xD M45xC Only Support Channel 0 7 0xXXXX_XXXX 31 30 29 28 27 26 25 24 DA 23 22 21 20 19 18 17 16 DA 15 14 13 1...

Page 391: ...21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 NEXT 7 6 5 4 3 2 1 0 NEXT Reserved Bits Description 31 16 Reserved Reserved 15 2 NEXT PDMA Next Descriptor Table Offset Address Register This field ind...

Page 392: ...of PDMA Channel n M45xD M45xC Only Support Channel 0 7 0xXXXX_XXXX 31 30 29 28 27 26 25 24 CURADDR 23 22 21 20 19 18 17 16 CURADDR 15 14 13 12 11 10 9 8 CURADDR 7 6 5 4 3 2 1 0 CURADDR Bits Descripti...

Page 393: ...EN4 CHEN3 CHEN2 CHEN1 CHEN0 Bits Description 31 12 Reserved Reserved 11 0 CHENn PDMA Channel Enable Bit Set this bit to 1 to enable PDMAn operation Channel cannot be active if it is not set as enabled...

Page 394: ...oftware reset writing 0xFFFF_FFFF to PDMA_STOP register By bit field 0 No effect 1 Stop PDMA transfer n When software set PDMA_STOP bit the operation will finish the on going transfer channel and then...

Page 395: ...SWREQ6 SWREQ5 SWREQ4 SWREQ3 SWREQ2 SWREQ1 SWREQ0 Bits Description 31 12 Reserved Reserved 11 0 SWREQn PDMA Software Request Register Write Only Set this bit to 1 to generate a software request to PDM...

Page 396: ...ion 31 12 Reserved Reserved 11 0 REQSTSn PDMA Channel Request Status Read Only This flag indicates whether channel n have a request or not no matter request from software or peripheral When PDMA contr...

Page 397: ...1 0 FPRISET7 FPRISET6 FPRISET5 FPRISET4 FPRISET3 FPRISET2 FPRISET1 FPRISET0 Bits Description 31 12 Reserved Reserved 11 0 FPRISETn PDMA Fixed Priority Setting Register Set this bit to 1 to enable fix...

Page 398: ...11 10 9 8 Reserved FPRICLR11 FPRICLR10 FPRICLR9 FPRICLR8 7 6 5 4 3 2 1 0 FPRICLR7 FPRICLR6 FPRICLR5 FPRICLR4 FPRICLR3 FPRICLR2 FPRICLR1 FPRICLR0 Bits Description 31 12 Reserved Reserved 11 0 FPRICLRn...

Page 399: ...22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved INTEN11 INTEN10 INTEN9 INTEN8 7 6 5 4 3 2 1 0 INTEN7 INTEN6 INTEN5 INTEN4 INTEN3 INTEN2 INTEN1 INTEN0 Bits Description 31 12 Reserved Rese...

Page 400: ...t 1 Peripheral request time out 29 3 Reserved Reserved 2 TEIF Table Empty Interrupt Flag Read Only This bit indicates that PDMA controller has finished each table transmission and the operation is Sto...

Page 401: ...4 13 12 11 10 9 8 Reserved ABTIF11 ABTIF10 ABTIF9 ABTIF8 7 6 5 4 3 2 1 0 ABTIF7 ABTIF6 ABTIF5 ABTIF4 ABTIF3 ABTIF2 ABTIF1 ABTIF0 Bits Description 31 12 Reserved Reserved 11 0 ABTIFn PDMA Read Write Ta...

Page 402: ...16 Reserved 15 14 13 12 11 10 9 8 Reserved TDIF11 TDIF10 TDIF9 TDIF8 7 6 5 4 3 2 1 0 TDIF7 TDIF6 TDIF5 TDIF4 TDIF3 TDIF2 TDIF1 TDIF0 Bits Description 31 12 Reserved Reserved 11 0 TDIFn Transfer Done F...

Page 403: ...4 3 2 1 0 TEMPTYF7 TEMPTYF6 TEMPTYF5 TEMPTYF4 TEMPTYF3 TEMPTYF2 TEMPTYF1 TEMPTYF0 Bits Description 31 12 Reserved Reserved 11 0 TEMPTYFn Scatter gather Table Empty Flag Register This bit indicates whi...

Page 404: ...23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved TXACTF11 TXACTF10 TXACTF9 TXACTF8 7 6 5 4 3 2 1 0 TXACTF7 TXACTF6 TXACTF5 TXACTF4 TXACTF3 TXACTF2 TXACTF1 TXACTF0 Bits Description 31 1...

Page 405: ...ister M45xD M45xC Only 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 TOUTEN7 TOUTEN6 TOUTEN5 TOUTEN4 TOUTEN3 TOUTEN2 TOUT...

Page 406: ...gister M45xD M45xC Only 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 TOUTIEN7 TOUTIEN6 TOUTIEN5 TOUTIEN4 TOUTIEN3 TOUTIE...

Page 407: ...e Address Register 0x2000_0000 31 30 29 28 27 26 25 24 SCATBA 23 22 21 20 19 18 17 16 SCATBA 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Description 31 16 SCATBA PDMA Scatter gather D...

Page 408: ...h0 Register M45xD M45xC Only 0xFFFF_FFFF 31 30 29 28 27 26 25 24 TOC1 23 22 21 20 19 18 17 16 TOC1 15 14 13 12 11 10 9 8 TOC0 7 6 5 4 3 2 1 0 TOC0 Bits Description 31 16 TOC1 Time out Counter for Chan...

Page 409: ...ster M45xD M45xC Only 0xFFFF_FFFF 31 30 29 28 27 26 25 24 TOC3 23 22 21 20 19 18 17 16 TOC3 15 14 13 12 11 10 9 8 TOC2 7 6 5 4 3 2 1 0 TOC2 Bits Description 31 16 TOC3 Time out Period Counter for Chan...

Page 410: ...ster M45xD M45xC Only 0xFFFF_FFFF 31 30 29 28 27 26 25 24 TOC5 23 22 21 20 19 18 17 16 TOC5 15 14 13 12 11 10 9 8 TOC4 7 6 5 4 3 2 1 0 TOC4 Bits Description 31 16 TOC5 Time out Period Counter for Chan...

Page 411: ...ster M45xD M45xC Only 0xFFFF_FFFF 31 30 29 28 27 26 25 24 TOC7 23 22 21 20 19 18 17 16 TOC7 15 14 13 12 11 10 9 8 TOC6 7 6 5 4 3 2 1 0 TOC6 Bits Description 31 16 TOC7 Time out Period Counter for Chan...

Page 412: ...served 20 16 REQSRC2 Channel 2 Request Source Selection This filed defines which peripheral is connected to PDMA channel 2 User can configure the peripheral setting by REQSRC2 Note The channel configu...

Page 413: ...14 Channel connects to PWM1_P1_RX 15 Channel connects to PWM1_P2_RX 16 Channel connects to PWM1_P3_RX 17 Channel connects to SPI0_RX 18 Channel connects to SPI1_RX 19 Channel connects to SPI2_RX 20 Ch...

Page 414: ...explanation of REQSRC0 23 21 Reserved Reserved 20 16 REQSRC6 Channel 6 Request Source Selection This filed defines which peripheral is connected to PDMA channel 6 User can configure the peripheral set...

Page 415: ...fer to the explanation of REQSRC0 23 21 Reserved Reserved 20 16 REQSRC10 Channel 10 Request Source Selection This filed defines which peripheral is connected to PDMA channel 10 User can configure the...

Page 416: ...timers with 24 bit up counter and one 8 bit prescale counter Independent clock source for each timer Provides one shot periodic toggle output and continuous counting operation modes 24 bit up counter...

Page 417: ...0 RSTCNT TIMERx_CTL 26 0 1 CNTPHASE TIMERx_EXTCTL 0 Reset counter Reset counter 00 01 10 T0_EXT T3_EXT Load Timer Wakeup 0 1 TMRx_CLK T0 T3 CAPEN TIMERx_EXTCTL 3 CAPEDGE TIMERx_EXTCTL 2 1 CAPFUNCS TIM...

Page 418: ...2 Clock Source of Timer Controller 6 8 4 Basic Configuration The peripheral clock source of Tiimer0 Timer3 can be enabled in TMRxCKEN CLK_APBCLK0 5 2 and selected as different frequency in TMR0SEL CL...

Page 419: ...ng operation of toggle output mode is almost the same as periodic mode except toggle output mode has associated T0 T3 or T0_EXT T3_EXT pin depending on TGLPINSEL TIMERx_CTL 22 setting to output signal...

Page 420: ...PHASE TIMERx_EXTCTL 0 bit In event counting mode the timer counting operation mode can be selected as one shot periodic and continuous counting mode to counts the counter value CNT TIMERx_CNT 23 0 for...

Page 421: ...de 6 8 5 9 Timer controller also provides reset counter function to reset CNT TIMERx_CNT 23 0 value while edge transition detected on Tx_EXT x 0 3 In this mode most the settings are the same as event...

Page 422: ...pulse as PWM external clock source When the TRGDAC TIMERx_CTL 20 is set if the timer interrupt signal is generated the timer controller will trigger DAC to start converter When the TRGEADC TIMERx_CTL...

Page 423: ...R W Timer1 Compare Register 0x0000_0000 TIMER1_INTS TS TMR_BA01 0x28 R W Timer1 Interrupt Status Register 0x0000_0000 TIMER1_CNT TMR_BA01 0x2C R Timer1 Data Register 0x0000_0000 TIMER1_CAP TMR_BA01 0x...

Page 424: ...rupt Status Register 0x0000_0000 TIMER3_CNT TMR_BA23 0x2C R Timer3 Data Register 0x0000_0000 TIMER3_CAP TMR_BA23 0x30 R Timer3 Capture Data Register 0x0000_0000 TIMER3_EXT CTL TMR_BA23 0x34 R W Timer3...

Page 425: ...ICEDEBUG ICE Debug Mode Acknowledge Disable Write Protect 0 ICE debug mode acknowledgement effects TIMER counting TIMER counter will be held while CPU is held by ICE 1 ICE debug mode acknowledgement D...

Page 426: ...nable Bit If this bit is set to 1 while timer interrupt flag TIF TIMERx_INTSTS 0 is 1 and INTEN TIMERx_CTL 29 is enabled the timer interrupt signal will generate a wake up trigger event to CPU 0 Wake...

Page 427: ...ll trigger PWM 18 TRGSSEL Trigger Source Select Bit This bit is used to select trigger source is from Timer time out interrupt signal or capture interrupt signal 0 Timer time out interrupt signal is u...

Page 428: ...ion 31 24 Reserved Reserved 23 0 CMPDAT Timer Compared Value CMPDAT is a 24 bit compared value register When the internal 24 bit up counter value is equal to CMPDAT value the TIF TIMERx_INTSTS 0 Timer...

Page 429: ...29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TWKF TIF Bits Description 31 2 Reserved Reserved 1 TWKF Timer Wake up Flag This bit...

Page 430: ..._BA23 0x2C R Timer3 Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CNT 15 14 13 12 11 10 9 8 CNT 7 6 5 4 3 2 1 0 CNT Bits Description 31 24 Reserved Reserved 23 0 C...

Page 431: ...000_0000 TIMER3_CAP TMR_BA23 0x30 R Timer3 Capture Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CAPDAT 15 14 13 12 11 10 9 8 CAPDAT 7 6 5 4 3 2 1 0 CAPDAT Bits De...

Page 432: ...Bit 0 Tx x 0 3 pin de bounce Disabled 1 Tx x 0 3 pin de bounce Enabled Note If this bit is enabled the edge detection of Tx pin is detected with de bounce circuit 6 CAPDBEN Timer External Capture Pin...

Page 433: ...e Bit This bit enables the Tx_EXT pin 0 Tx_EXT x 0 3 pin Disabled 1 Tx_EXT x 0 3 pin Enabled 2 1 CAPEDGE Timer External Capture Pin Edge Detect 00 A Falling edge on Tx_EXT x 0 3 pin will be detected 0...

Page 434: ...2 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CAPIF Bits Description 31 1 Reserved Reserved 0 CAPIF Timer External Capture Interrupt Flag This bit indicates the...

Page 435: ...ntrol unit it supports polarity output independent pin mask and brake functions The PWM generator also supports input capture function It supports latch PWM counter value to corresponding register whe...

Page 436: ...ed Supports trigger EADC DAC on the following events PWM counter match zero period value or compared value PWM counter match free trigger comparator compared value only for EADC Capture Function Featu...

Page 437: ...iagram PWM system clock frequency can be set equal or double to HCLK frequency as Figure 6 9 2 the detail register setting please refer to Table 6 13 Each PWM generator has three clock source inputs e...

Page 438: ...d PWM_CH5 counters both come from the same clock source and prescaler When counter count to 0 PERIOD PWM_PERIODn 15 0 or equal to comparator events will be generated These events are passed to corresp...

Page 439: ...16 16 PWM0_CH5 Counter0 16bits Comparator0 16bits Counter1 16bits Comparator1 16bits Counter2 16bits Comparator2 16bits Counter3 16bits Comparator3 16bits Counter4 16bits Comparator4 16bits Counter5...

Page 440: ...M0_CLK4 a i t denotes interrupt events denotes trigger events denotes interrupt trigger and pulse generate events Note Figure 6 9 5 PWM Complementary Mode Architecture Diagram 6 9 4 Basic Configuratio...

Page 441: ...generates zero point event when the counter counts to 0 and generates period point event when counting to PERIOD The Figure 6 9 7 shows an example of up counter wherein PWM period time PERIOD 1 x PWM...

Page 442: ...DIRF PWM Counter CNT 0 1 2 3 4 3 1 2 0 1 2 3 4 3 1 2 0 5 6 7 6 4 5 1 2 3 4 PWM Period PERIOD 4 PERIOD 7 PWM Period zero point event center point event Figure 6 9 9 PWM Up Down Counter Type PWM Compar...

Page 443: ...will load register value to the buffer register according to the loading mode timing The hardware action is based on the buffer value This can prevent asynchronously operation problem due to software...

Page 444: ...ion or down counts from PERIOD to zero in the down counter operation or up counts from zero to PERIOD and then down counts to zero in the up down counter operation Figure 6 9 12 shows period loading t...

Page 445: ...s PERIOD or CMPDAT If the updated PERIOD value is less than current counter value counter will count wraparound Immediately loading mode has the highest priority If IMMLDENn has been set other loading...

Page 446: ...Every channel n s load window is opened by setting the corresponding LOADn PWM_LOAD 5 0 to 1 and hardware will close the window at the end of PWM period Window loading mode can work with center loadin...

Page 447: ...ch corresponds to PWM channel n set to 1 and in up down counter type CMPDAT will load to CMPBUFn in center of a period that is counter counts to PERIOD PERIOD loading timing is the same as period load...

Page 448: ...prescaler and counter start running After PWM counter counted a period counter value will keep in zero Software needs to write new CMPDAT to re start next one shot If one shot counter still running wr...

Page 449: ...to comparator point in three types As to up down counter type there are two counter equal comparator points one at up count and the other at down count Besides Complementary mode has two comparators...

Page 450: ...nter type Table 6 14 down counter type Table 6 15 and up down counter type Table 6 16 By using event priority user can easily generate 0 to 100 duty pulse as shown in Figure 6 9 18 0 1 2 3 4 3 2 1 0 1...

Page 451: ...e PWM is operating in independent mode independent mode is enabled when channel n corresponding OUTMODEn PWM_CTL1 26 24 bit is set to 0 In this mode six PWM channels PWM_CH0 PWM_CH1 PWM_CH2 PWM_CH3 PW...

Page 452: ...o output functions group and synchronous functions for advanced output control Group function forces the PWM_CH2 and PWM_CH4 synchronous with PWM_CH0 generator and forces the PWM_CH3 and PWM_CH5 synch...

Page 453: ...put signal will be filtered by a 3 bit noise filter as Figure 6 9 22 In addition it can be inversed by setting the bit SINPINV PWM_SYNC 23 to realize the polarity setup for the input signal The noise...

Page 454: ...ame time user have to set the PWM Synchronous Start Control Register PWM_SSCTL 5 0 to enable the channel counters which are planned to sync together followed by setting the PWM Synchronous Start Trigg...

Page 455: ...nous Function with SINSRC 0 PWM Output Control 6 9 5 20 After PWM pulse generation there are four to six steps to control the output of PWM channels In independent mode there are Mask Brake Pin Polari...

Page 456: ...ices from the burn out damage Hence the dead time control is a crucial mechanism to the proper operation of the complementary system By setting corresponding channel n DTEN PWM_DTCTLn 16 bit to enable...

Page 457: ...annel n output will be overridden The PWM_MSK register contains six bits MSKDATn PWM_MSK 5 0 The bit value of the MSKDATn determines the state value of the PWM channel n output when the channel is ove...

Page 458: ...event occurs Each complementary channel pair shares a PWM brake function as shown Figure 6 9 30 To control paired channels to output safety state user can setup BRKAEVEN PWM_BRKCTL0_1 17 16 for even...

Page 459: ...n the event occurs both of the BRKEIF0 and BRKEIF1 flags are set and BRKESTS0 and BRKESTS1 are also set to indicate brake state of PWM_CH0 and PWM_CH1 For the first occurring event software writes 1 t...

Page 460: ...CH0 BRKLIF1 BRKLIF0 s w clear BRKLSTS0 BRKLSTS1 s w clear PWM_CH1 No matter BRKLIF0 or BRKLIF1 clear or not while no brake event occur brake state resume at next start of PWM period Note Output Brake...

Page 461: ...rake Function Edge Detect Brake Source Level Detect Brake Source Brake System Fail SYSEBEN PWM_BRKCTL0 7 ACMP0_O ACMP1_O BRKP0LEN PWM_BRKCTL0 12 Brake Noise Filter BRKP1LEN PWM_BRKCTL0 13 CPO0LBEN PWM...

Page 462: ...37 The 1 st PWM interrupt PWM_INT comes from PWM complementary pair events The counter can generate the Zero point Interrupt Flag ZIFn PWM_INTSTS0 5 0 and the Period point Interrupt Flag PIFn PWM_INTS...

Page 463: ...CNT0_1 1 times interrupt events occurred IFCNT0_1 IFAEN0_1 zero point flag PWM_CNT0 2 0 1 2 3 4 3 1 2 0 1 2 3 4 3 1 2 0 5 6 7 6 4 5 1 2 3 4 IFSEL0_1 0 PWM_PERIOD0 4 7 IFAIF0_1 PWM_INT Figure 6 9 36 PW...

Page 464: ...CMPDIF0 PWM_INTSTS0 24 ZIEN1 PWM_INTEN0 1 ZIF1 PWM_INTSTS0 1 PIEN1 PWM_INTEN0 9 PIF1 PWM_INTSTS0 9 CMPUIEN1 PWM_INTEN0 17 CMPUIF1 PWM_INTSTS0 17 CMPDIEN1 PWM_INTEN0 25 CMPDIF1 PWM_INTSTS0 25 CAPRIEN0...

Page 465: ...Figure 6 9 38 is an example of PWM_CH0 and PWM_CH1 PWM can trigger EADC to start conversion in different timings by setting PERIOD CMPDAT and FTCMPDAT FTCMPDAT only use to trigger EADC Figure 6 9 39...

Page 466: ...to those for triggerring EADC However DAC triggering function does not include the triggering events from comparison with FTCMPDAT that is there are no trigger points the same as FTCMPDATU and FTCMPD...

Page 467: ...PPAT PWM_RCAPDAT0 15 0 FCAPDAT PWM_FCAPDAT0 15 0 CAPEN0 PWM_CAPCTL 0 CAPINV0 PWM_CAPCTL 8 CAPINEN0 PWM_CAPINEN 0 PWM_CH0 RCRLDEN0 PWM_CAPCTL 16 FCRLDEN0 PWM_CAPCTL 24 Note denotes rising edge detect d...

Page 468: ...set to 1 by hardware to indicate the CRLIF overrunning Also if the falling latch happens again the same hardware operation occurs for the interrupt flag CFLIF and the Over run status CFLIFOVn PWM_CAPS...

Page 469: ...t The complement pair channels share a PDMA channel Therefore a selection bit CHSELn_m CHSEL0_1 PWM_PDMACTL 4 CHSEL2_3 PWM_PDMACTL 12 and CHSEL4_5 PWM_PDMACTL 20 is used to decide either channel n or...

Page 470: ...1 PWMx_BA 0x14 R W PWM Clock Pre scale Register 0 0x0000_0000 PWM_CLKPSC2 _3 x 0 1 PWMx_BA 0x18 R W PWM Clock Pre scale Register 2 0x0000_0000 PWM_CLKPSC4 _5 x 0 1 PWMx_BA 0x1C R W PWM Clock Pre scale...

Page 471: ...Mx_BA 0x74 R W PWM Dead Time Control Register 2 0x0000_0000 PWM_DTCTL4_ 5 x 0 1 PWMx_BA 0x78 R W PWM Dead Time Control Register 4 0x0000_0000 PWM_PHS0_1 x 0 1 PWMx_BA 0x80 R W PWM Counter Phase Regist...

Page 472: ...egister 4 0x0000_0000 PWM_POLCTL x 0 1 PWMx_BA 0xD4 R W PWM Pin Polar Inverse Register 0x0000_0000 PWM_POEN x 0 1 PWMx_BA 0xD8 R W PWM Output Enable Register 0x0000_0000 PWM_SWBRK x 0 1 PWMx_BA 0xDC W...

Page 473: ...le Register 0x0000_0000 PWM_CAPCTL x 0 1 PWMx_BA 0x204 R W PWM Capture Control Register 0x0000_0000 PWM_CAPSTS x 0 1 PWMx_BA 0x208 R PWM Capture Status Register 0x0000_0000 PWM_RCAPDAT 0 x 0 1 PWMx_BA...

Page 474: ...Register 0x0000_0000 PWM_PDMACA P4_5 x 0 1 PWMx_BA 0x248 R PWM Capture Channel 45 PDMA Register 0x0000_0000 PWM_CAPIEN x 0 1 PWMx_BA 0x250 R W PWM Capture Interrupt Enable Register 0x0000_0000 PWM_CAP...

Page 475: ...WM CMPDAT4 Buffer 0x0000_0000 PWM_CMPBUF5 x 0 1 PWMx_BA 0x330 R PWM CMPDAT5 Buffer 0x0000_0000 PWM_FTCBUF0 _1 x 0 1 PWMx_BA 0x340 R PWM FTCMPDAT0_1 Buffer 0x0000_0000 PWM_FTCBUF2 _3 x 0 1 PWMx_BA 0x34...

Page 476: ...ot Note This register is write protected Refer to SYS_REGLCTL register 30 DBGHALT ICE Debug Mode Counter Halt Write Protect If counter halt is enabled PWM all counters will keep current value until ex...

Page 477: ...by setting CTRLD bit 1 PERIOD will load to PBUF at the end point of each period CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set The valid reload window is s...

Page 478: ...1 CNTTYPE0 Bits Description 31 27 Reserved Reserved 26 24 OUTMODEn PWM Output Mode Each bit n controls the output mode of corresponding PWM channel n 0 PWM independent mode 1 PWM complementary mode No...

Page 479: ...rement after synchronizing 23 SINPINV SYNC Input Pin Inverse 0 The state of pin SYNC is passed to the positive edge detector 1 The inversed state of pin SYNC is passed to the positive edge detector 22...

Page 480: ...01 Counter equal to 0 10 Counter equal to PWM_CMPDATm m denotes 1 3 5 11 SYNC_OUT will not be generated 7 3 Reserved Reserved 2 0 PHSENn SYNC Phase Enable Bit Each bit n controls corresponding PWM cha...

Page 481: ...Software Control Synchronization Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SWSYNC4 SWSYNC2 SWSYNC0...

Page 482: ...9 Reserved Reserved 18 16 ECLKSRC4 PWM_CH45 External Clock Source Select 000 PWMx_CLK x denotes 0 or 1 001 TIMER0 overflow 010 TIMER1 overflow 011 TIMER2 overflow 100 TIMER3 overflow Others Reserved 1...

Page 483: ...18 R W PWM Clock Pre scale Register 2 0x0000_0000 PWM_CLKPS C4_5 PWMx_BA 0x1C R W PWM Clock Pre scale Register 4 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13...

Page 484: ...Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CNTEN5 CNTEN4 CNTEN3 CNTEN2 CNTEN1 CNTEN0 Bits Descripti...

Page 485: ...egister 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CNTCLR5 CNTCLR4 CNTCLR3 CNTCLR2 CNTCLR1 CNTCLR0 Bits Descr...

Page 486: ...8 Reserved 7 6 5 4 3 2 1 0 Reserved LOAD5 LOAD4 LOAD3 LOAD2 LOAD1 LOAD0 Bits Description 31 6 Reserved Reserved 5 0 LOADn Re load PWM Comparator Register CMPDAT Control Bit This bit is software write...

Page 487: ...PWM Period Register 4 0x0000_0000 PWM_PERIO D5 PWMx_BA 0x44 R W PWM Period Register 5 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 PERIOD 7 6 5 4...

Page 488: ...M Comparator Register 4 0x0000_0000 PWM_CMPDA T5 PWMx_BA 0x64 R W PWM Comparator Register 5 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CMP 7 6...

Page 489: ...0 Dead time clock source from PWM_CLK 1 Dead time clock source from prescaler output Note This register is write protected Refer to REGWRPROT register 23 17 Reserved Reserved 16 DTEN Dead time Insert...

Page 490: ...x0000_0000 PWM_PHS2_3 PWMx_BA 0x84 R W PWM Counter Phase Register 2 0x0000_0000 PWM_PHS4_5 PWMx_BA 0x88 R W PWM Counter Phase Register 4 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18...

Page 491: ...PWM_CNT3 PWMx_BA 0x9C R PWM Counter Register 3 0x0000_0000 PWM_CNT4 PWMx_BA 0xA0 R PWM Counter Register 4 0x0000_0000 PWM_CNT5 PWMx_BA 0xA4 R PWM Counter Register 5 0x0000_0000 31 30 29 28 27 26 25 24...

Page 492: ...rved 27 16 PRDPCTLn PWM Period Center Point Control Each bit n controls the corresponding PWM channel n 00 Do nothing 01 PWM period center point output Low 10 PWM period center point output High 11 PW...

Page 493: ...ntrol Each bit n controls the corresponding PWM channel n 00 Do nothing 01 PWM compare down point output Low 10 PWM compare down point output High 11 PWM compare down point output Toggle PWM can contr...

Page 494: ...20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved MSKEN5 MSKEN4 MSKEN3 MSKEN2 MSKEN1 MSKEN0 Bits Description 31 6 Reserved Reserved 5 0 MSKENn PWM Mask Enable Bits Each...

Page 495: ...27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved MSKDAT5 MSKDAT4 MSKDAT3 MSKDAT2 MSKDAT1 MSKDAT0 Bits Description 31 6 Reserved Reserved 5...

Page 496: ...g 0 Brake 1 pin source come from PWM1_BRAKE1 1 Brake 1 pin source come from PWM0_BRAKE1 23 17 Reserved Reserved 16 BK0SRC Brake 0 Pin Source Select M45xD M45xC Only For PWM0 setting 0 Brake 0 pin sour...

Page 497: ...e detector 1 The inversed state of pin PWMx_BRAKE10 is passed to the negative edge detector 6 4 BRK0FCNT Brake 0 Edge Detector Filter Count The register bits control the Brake0 filter counter to count...

Page 498: ...ake Function 0 Enable Bit 0 Brake Function triggered by Core lockup detection Disabled 1 Brake Function triggered by Core lockup detection Enabled 2 RAMBRKEN SRAM Parity Error Detection Trigger PWM Br...

Page 499: ...hannel output low level when level detect brake happened 11 PWM odd channel output high level when level detect brake happened Note This register is write protected Refer to SYS_REGLCTL register 17 16...

Page 500: ...brake source Disabled 1 System Fail condition as edge detect brake source Enabled Note This register is write protected Refer to SYS_REGLCTL register 6 Reserved Reserved 5 BRKP1EEN PWMx_BRAKE1 Pin As...

Page 501: ...x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved PINV5 PINV4 PINV3 PINV2 PINV1 PINV0 Bits Description 31 6 Reserved...

Page 502: ...D8 R W PWM Output Enable Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved POEN5 POEN4 POEN3 POEN2 POEN1 PO...

Page 503: ...scription 31 11 Reserved Reserved 10 8 BRKLTRGn PWM Level Brake Software Trigger Write Only Write Protect Each bit n controls the corresponding PWM pair n Write 1 to this bit will trigger level brake...

Page 504: ...In complementary mode CMPDIEN1 3 5 use as another CMPDIEN for channel 0 2 4 23 IFAIEN4_5 PWM_CH4 5 Interrupt Flag Accumulator Interrupt Enable Bit 0 Interrupt Flag accumulator interrupt Disabled 1 Int...

Page 505: ...ble Bit 0 Interrupt Flag accumulator interrupt Disabled 1 Interrupt Flag accumulator interrupt Enabled 6 Reserved Reserved 5 0 ZIENn PWM Zero Point Interrupt Enable Bits Each bit n controls the corres...

Page 506: ...te This register is write protected Refer to SYS_REGLCTL register 8 BRKLIEN0_1 PWM Level detect Brake Interrupt Enable Bit for Channel0 1 Write Protect 0 Level detect Brake interrupt for channel0 1 Di...

Page 507: ...de CMPDIF1 3 5 use as another CMPDIF for channel 0 2 4 23 IFAIF4_5 PWM_CH4 5 Interrupt Flag Accumulator Interrupt Flag Flag is set by hardware when condition match IFSEL4_5 in PWM_IFA register softwar...

Page 508: ...condition match IFSEL0_1 in PWM_IFA register software can clear this bit by writing 1 to it 6 Reserved Reserved 5 0 ZIFn PWM Zero Point Interrupt Flag Each bit n controls the corresponding PWM channe...

Page 509: ...channel4 level detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel4 at brake state Note This bit is read only and auto cleared by hardwar...

Page 510: ...annel4 at brake state writing 1 to clear 19 BRKESTS3 PWM Channel3 Edge detect Brake Status 0 PWM channel3 edge detect brake state is released 1 When PWM channel3 edge detect brake detects a falling ed...

Page 511: ...upt Flag Write Protect 0 PWM channel5 edge detect brake event do not happened 1 When PWM channel5 edge detect brake event happened this bit is set to 1 writing 1 to clear Note This register is write p...

Page 512: ...512 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL 1 When PWM channel0 edge detect brake event happened this bit is set to 1 writing 1 to clear Note This register is write protected Refer to...

Page 513: ...channel 4 010 CNT equal to CMPU in channel 4 011 CNT equal to CMPD in channel 4 100 CNT equal to Zero in channel 5 101 CNT equal to PERIOD in channel 5 110 CNT equal to CMPU in channel 5 111 CNT equa...

Page 514: ...errupt flag accumulator Disabled 1 PWM_CH0 and PWM_CH1 interrupt flag accumulator Enabled 6 4 IFSEL0_1 PWM_CH0 and PWM_CH1 Interrupt Flag Accumulator Source Select 000 CNT equal to Zero in channel 0 0...

Page 515: ...annel n Note1 This bit should keep at 0 when PWM counter operating in up counter type Note2 In complementary mode CDTRGE1 3 5 use as another CDTRGE for channel 0 2 4 23 22 Reserved Reserved 21 16 CUTR...

Page 516: ...M451 SERIES TECHNICAL REFERENCE MANUAL 1 PWM period point trigger DAC function Enabled PWM can trigger EADC DAC DMA to start action when PWM counter down count to zero if this bit is set to1 Each bit...

Page 517: ...ed 27 24 TRGSEL3 PWM_CH3 Trigger EADC Source Select 0000 PWM_CH2 zero point 0001 PWM_CH2 period point 0010 PWM_CH2 zero or period point 0011 PWM_CH2 up count CMPDAT point 0100 PWM_CH2 down count CMPDA...

Page 518: ...eserved Reserved 11 8 TRGSEL1 PWM_CH1 Trigger EADC Source Select 0000 PWM_CH0 zero point 0001 PWM_CH0 period point 0010 PWM_CH0 zero or period point 0011 PWM_CH0 up count CMPDAT point 0100 PWM_CH0 dow...

Page 519: ...H1 zero or period point 1000 PWM_CH1 up count CMPDAT point 1001 PWM_CH1 down count CMPDAT point 1010 PWM_CH0 up count free CMPDAT point 1011 PWM_CH0 down count free CMPDAT point 1100 PWM_CH2 up count...

Page 520: ...ed 14 12 Reserved Reserved 11 8 TRGSEL5 PWM_CH5 Trigger EADC Source Select 0000 PWM_CH4 zero point 0001 PWM_CH4 period point 0010 PWM_CH4 zero or period point 0011 PWM_CH4 up count CMPDAT point 0100 P...

Page 521: ...int 0100 PWM_CH4 down count CMPDAT point 0101 PWM_CH5 zero point 0110 PWM_CH5 period point 0111 PWM_CH5 zero or period point 1000 PWM_CH5 up count CMPDAT point 1001 PWM_CH5 down count CMPDAT point 101...

Page 522: ...0x104 R W PWM Free Trigger Compare Register 2 0x0000_0000 PWM_FTCMP DAT4_5 PWMx_BA 0x108 R W PWM Free Trigger Compare Register 4 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 R...

Page 523: ...20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SSEN5 SSEN4 SSEN3 SSEN2 SSEN1 SSEN0 Bits Description 31 6 Reserved Reserved 5 0 SSENn PWM Synchronous Start Function Ena...

Page 524: ...served 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CNTSEN Bits Description 31 1 Reserved Reserved 0 CNTSEN PWM Counter Synchronous Start Enable Bit Write Only PMW counter synchronous enabl...

Page 525: ...rred software can write 1 to clear this bit 23 22 Reserved Reserved 21 16 ADCTRGFn EADC Start of Conversion Flag Each bit n controls the corresponding PWM channel n 0 Indicates no EADC start of conver...

Page 526: ...19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CAPINEN5 CAPINEN4 CAPINEN3 CAPINEN2 CAPINEN1 CAPINEN0 Bits Description 31 6 Reserved Reserved 5 0 CAPINENn Capture Input En...

Page 527: ...M channel n 0 Falling capture reload counter Disabled 1 Falling capture reload counter Enabled 23 22 Reserved Reserved 21 16 RCRLDENn Rising Capture Reload Enable Bits Each bit n controls the correspo...

Page 528: ...OV1 CRLIFOV0 Bits Description 31 14 Reserved Reserved 13 8 CFLIFOVn Capture Falling Latch Interrupt Flag Overrun Status Read Only This flag indicates if falling latch happened when the corresponding C...

Page 529: ...apture Data Register 2 0x0000_0000 PWM_RCAPD AT3 PWMx_BA 0x224 R PWM Rising Capture Data Register 3 0x0000_0000 PWM_RCAPD AT4 PWMx_BA 0x22C R PWM Rising Capture Data Register 4 0x0000_0000 PWM_RCAPD A...

Page 530: ...pture Data Register 2 0x0000_0000 PWM_FCAPD AT3 PWMx_BA 0x228 R PWM Falling Capture Data Register 3 0x0000_0000 PWM_FCAPD AT4 PWMx_BA 0x230 R PWM Falling Capture Data Register 4 0x0000_0000 PWM_FCAPD...

Page 531: ...er the PWM_RCAPDAT4 5 or PWM_FCAPDAT4 5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 11 0 PWM_FCAPDAT4 5 is the first captured data to memory 1 PWM_RCAPDAT4 5 is the fi...

Page 532: ...rved Reserved 4 CHSEL0_1 Select Channel 0 1 to Do PDMA Transfer 0 Channel0 1 Channel1 3 CAPORD0_1 Capture Channel 0 1 Rising Falling Order Set this bit to determine whether the PWM_RCAPDAT0 1 or PWM_F...

Page 533: ...0000 PWM_PDMAC AP2_3 PWMx_BA 0x244 R PWM Capture Channel 23 PDMA Register 0x0000_0000 PWM_PDMAC AP4_5 PWMx_BA 0x248 R PWM Capture Channel 45 PDMA Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved...

Page 534: ...N1 CAPRIEN0 Bits Description 31 14 Reserved Reserved 13 8 CAPFIENn PWM Capture Falling Latch Interrupt Enable Bit Each bit n controls the corresponding PWM channel n 0 Capture falling edge latch inter...

Page 535: ...Interrupt Flag This bit is writing 1 to clear Each bit n controls the corresponding PWM channel n 0 No capture falling latch condition happened 1 Capture falling latch condition happened this flag wil...

Page 536: ...x0000_0000 PWM_PBUF2 PWMx_BA 0x30C R PWM PERIOD2 Buffer 0x0000_0000 PWM_PBUF3 PWMx_BA 0x310 R PWM PERIOD3 Buffer 0x0000_0000 PWM_PBUF4 PWMx_BA 0x314 R PWM PERIOD4 Buffer 0x0000_0000 PWM_PBUF5 PWMx_BA...

Page 537: ...0_0000 PWM_CMPBU F2 PWMx_BA 0x324 R PWM CMPDAT2 Buffer 0x0000_0000 PWM_CMPBU F3 PWMx_BA 0x328 R PWM CMPDAT3 Buffer 0x0000_0000 PWM_CMPBU F4 PWMx_BA 0x32C R PWM CMPDAT4 Buffer 0x0000_0000 PWM_CMPBU F5...

Page 538: ...FTCMPDAT0_1 Buffer 0x0000_0000 PWM_FTCBU F2_3 PWMx_BA 0x344 R PWM FTCMPDAT2_3 Buffer 0x0000_0000 PWM_FTCBU F4_5 PWMx_BA 0x348 R PWM FTCMPDAT4_5 Buffer 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 2...

Page 539: ...FTCMD4 FTCMD2 FTCMD0 7 6 5 4 3 2 1 0 Reserved FTCMU4 FTCMU2 FTCMU0 Bits Description 31 11 Reserved Reserved 10 8 FTCMDn PWM FTCMPDAT Down Indicator Indicator will be set to high when FTCMPDATn equal t...

Page 540: ...ay period including 1026 130 18 or 3 WDT_CLK reset delay period Supports to force WDT enabled after chip powered on or reset by setting CWDTEN 2 0 in Config0 register Supports WDT time out wake up fun...

Page 541: ...can be selected by setting TOUTSEL WDT_CTL 10 8 When the WDT up counter reaches the TOUTSEL WDT_CTL 10 8 settings WDT time out interrupt will occur then WDT time out interrupt flag IF WDT_CTL 3 will...

Page 542: ...TD Watchdog Reset Delay Period Selectable 3 18 130 1026 TWDT delay period controlled by RSTDSEL WDT_ALTCTL 1 0 TRST Watchdog Reset Period 63 TWDT WDT_CLK IF 1 RSTF 1 if RSTEN 1 IF RSTF Figure 6 10 3 W...

Page 543: ...L 6 10 7 Register Map R read only W write only R W both read and write Register Offset R W Description Reset Value WDT Base Address WDT_BA 0x4004_0000 WDT_CTL WDT_BA 0x00 R W WDT Control Register 0x00...

Page 544: ...ICE or not Note This bit is write protected Refer to the SYS_REGLCTL register 30 11 Reserved Reserved 10 8 TOUTSEL WDT Time out Interval Selection Write Protect These three bits select the time out in...

Page 545: ...protected Refer to the SYS_REGLCTL register Note2 Chip can be woken up by WDT time out interrupt signal generated only if WDT clock source is selected to LIRC or LXT 3 IF WDT Time out Interrupt Flag...

Page 546: ...eserved 1 0 RSTDSEL WDT Reset Delay Selection Write Protect When WDT time out happened user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT WDT_CTL 0 to prevent WDT time...

Page 547: ...TDAT and 6 bit compare value CMPDAT to make the WWDT time out window period flexible Supports 4 bit value PSCSEL to programmable maximum 11 bit prescale counter period of WWDT counter 6 11 3 Block Dia...

Page 548: ...o define different WWDT time out intervals The clock source of 6 bit WWDT is based on system clock divide 2048 HCLK 2048 or 10 kHz internal low speed RC oscillator LIRC with a programmable 11 bit pres...

Page 549: ...IF WWDT_STATUS 0 is generated user must reload WWDT counter value to 0x3F by writing 0x00005AA5 to WWDT_RLDCNT register and also to prevent WWDT counter value reached to 0 and generate WWDT reset syst...

Page 550: ...y 4 2018 Page 550 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL PSCSEL Prescale Value Valid CMPDAT Value 0000 1 0x3 0x3F 0001 2 0x2 0x3F Others Others 0x0 0x3F Table 6 19 CMPDAT Setting Limi...

Page 551: ...write Register Offset R W Description Reset Value WWDT Base Address WWDT_BA 0x4004_0100 WWDT_RLDC NT WWDT_BA 0x00 W WWDT Reload Counter Register 0x0000_0000 WWDT_CTL WWDT_BA 0x04 R W WWDT Control Regi...

Page 552: ...NT 23 22 21 20 19 18 17 16 RLDCNT 15 14 13 12 11 10 9 8 RLDCNT 7 6 5 4 3 2 1 0 RLDCNT Bits Description 31 0 RLDCNT WWDT Reload Counter Register Writing 0x00005AA5 to this register will reload the WWDT...

Page 553: ...load window Note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT If user writes WWDT_RLDCNT register when current WWDT counte...

Page 554: ...K 1111 Pre scale is 2048 Max time out period is 2048 64 WWDT_CLK 7 2 Reserved Reserved 1 INTEN WWDT Interrupt Enable Control Bit If this bit is enabled the WWDT counter compare match interrupt signal...

Page 555: ...1 0 Reserved WWDTRF WWDTIF Bits Description 31 2 Reserved Reserved 1 WWDTRF WWDT Timer out Reset Flag This bit indicates the system has been reset by WWDT time out reset or not 0 WWDT time out reset d...

Page 556: ...eset Value WWDT_CNT WWDT_BA 0x0C R WWDT Counter Value Register 0x0000_003F 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CNT...

Page 557: ...r in RTC_CAL year month day for RTC time and calendar check Supports alarm time hour minute second and calendar year month day settings in RTC_TALM and RTC_CALM Supports alarm time hour minute second...

Page 558: ...CLK_CLKSEL3 8 LXT TAMPER VBAT SNPDIF RTC_INTSTS 2 INIT INIT RWEN LEAPYEAR CLKFMT WEEKDAY SPRCTL Figure 6 12 1 RTC Block Diagram 6 12 4 Basic Configuration The RTC controller clock source is enabled b...

Page 559: ...r RWENF 1 RWENF 0 RTC_INIT R W R W RTC_RWEN R W R W RTC_FREQADJ R W Not available RTC_TIME R W R RTC_CAL R W R RTC_CLKFMT R W R W RTC_WEEKDAY R W R RTC_TALM R W Not available RTC_CALM R W Not availabl...

Page 560: ...lock measured 32765 27 Hz 32768 Hz Integer part 32765 0x7FFD If integer part of detected value is 32768 RTC_FREQADJ 11 8 is assigned to be 0111b Now that integer part of detected value is 32765 the co...

Page 561: ...dically in the period selected by RTC_TICK 2 0 settings Alarm Interrupt 6 12 5 9 When the real time and calendar message in RTC_TIME and RTC_CAL registers are equal to alarm time and calendar values i...

Page 562: ...0x2 RTC_TIME 14 8 0x59 TENMIN RTC_TIME 14 12 is 0x5 MIN RTC_TIME 11 8 is 0x9 RTC_TIME 6 0 0x30 TENSEC RTC_TIME 6 4 is 0x3 SEC RTC_TIME 3 0 is 0x0 6 Which power domain the register is in Register Powe...

Page 563: ...SPRRWEN RTC_SPRCTL 2 before writing one of 20 spare registers RTC_SPR0 RTC_SPR19 User could read SPRRWRDY RTC_SPRCTL 7 to check if data has been written into registers or not User could only access th...

Page 564: ...pin is controlled by RTC or GPIO module The PF 1 X32I and PF 2 TAMPER pins are controlled by CTLSEL in RTC_LXTICTL 3 and RTC_TAMPCTL 3 respectively CTLSEL RTC PFx_OPMODE GPIO PFx_MODE GPIO PFx_DOUT RT...

Page 565: ...A 0x24 R RTC Leap Year Indicator Register 0x0000_0000 RTC_INTEN RTC_BA 0x28 R W RTC Interrupt Enable Register 0x0000_0000 RTC_INTSTS RTC_BA 0x2C R W RTC Interrupt Indicator Register 0x0000_0000 RTC_TI...

Page 566: ...SPR15 RTC_BA 0x7C R W RTC Spare Register 15 0x0000_0000 RTC_SPR16 RTC_BA 0x80 R W RTC Spare Register 16 0x0000_0000 RTC_SPR17 RTC_BA 0x84 R W RTC Spare Register 17 0x0000_0000 RTC_SPR18 RTC_BA 0x88 R...

Page 567: ...16 INIT 15 14 13 12 11 10 9 8 INIT 7 6 5 4 3 2 1 0 INIT INIT 0 ACTIVE Bits Description 31 1 INIT 31 1 RTC Initiation When RTC block is powered on RTC is at reset state User has to write a number 0x a...

Page 568: ...16 Reserved RWENF 15 14 13 12 11 10 9 8 RWEN 7 6 5 4 3 2 1 0 RWEN Bits Description 31 17 Reserved Reserved 16 RWENF RTC Register Access Enable Flag Read Only 0 RTC register read write Disabled 1 RTC r...

Page 569: ...31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved INTEGER 7 6 5 4 3 2 1 0 Reserved FRACTION Bits Description 31 12 Reserved Reserved 11 8 INTEGER Intege...

Page 570: ...NSEC SEC Bits Description 31 22 Reserved Reserved 21 20 TENHR 10 hour Time Digit 0 2 When RTC runs as 12 hour time scale mode RTC_TIME 21 the high bit of TENHR 1 0 means AM PM indication If RTC_TIME 2...

Page 571: ...12 11 10 9 8 Reserved TENMON MON 7 6 5 4 3 2 1 0 Reserved TENDAY DAY Bits Description 31 24 Reserved Reserved 23 20 TENYEAR 10 Year Calendar Digit 0 9 19 16 YEAR 1 Year Calendar Digit 0 9 15 13 Reserv...

Page 572: ...election Register 0x0000_0001 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved 24HEN Bits Description 31 1 Reserved Reserved 0...

Page 573: ...WEEKD AY RTC_BA 0x18 R W RTC Day of the Week Register 0x0000_0006 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WEEKDAY Bits...

Page 574: ...git of Alarm Setting 0 2 When RTC runs as 12 hour time scale mode the high bit of TENHR RTC_TIME 21 means AM PM indication 19 16 HR 1 Hour Time Digit of Alarm Setting 0 9 15 Reserved Reserved 14 12 TE...

Page 575: ...erved 23 20 TENYEAR 10 Year Calendar Digit of Alarm Setting 0 9 19 16 YEAR 1 Year Calendar Digit of Alarm Setting 0 9 15 13 Reserved Reserved 12 TENMON 10 Month Calendar Digit of Alarm Setting 0 1 11...

Page 576: ...eset Value RTC_LEAPYE AR RTC_BA 0x24 R RTC Leap Year Indicator Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Res...

Page 577: ...21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SNPDIEN TICKIEN ALMIEN Bits Description 31 3 Reserved Reserved 2 SNPDIEN Snoop Detection Interrupt Enable Bit 0 Snoo...

Page 578: ...oop event is detected 1 Snoop event is detected Note Write 1 to clear this bit 1 TICKIF RTC Time Tick Interrupt Flag When RTC time tick happened this bit will be set to 1 and an interrupt will be gene...

Page 579: ...rved Reserved 2 0 TICK Time Tick Register These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request 000 Time tick is 1 second 001 Time tick is 1 2 second 010 Time tic...

Page 580: ...2 1 0 Reserved MTENHR MHR MTENMIN MMIN MTENSEC MSEC Bits Description 31 6 Reserved Reserved 5 MTENHR Mask 10 Hour Time Digit of Alarm Setting 0 2 4 MHR Mask 1 Hour Time Digit of Alarm Setting 0 9 3 M...

Page 581: ...rved MTENYEAR MYEAR MTENMON MMON MTENDAY MDAY Bits Description Reserved Reserved 5 MTENYEAR Mask 10 Year Calendar Digit of Alarm Setting 0 9 4 MYEAR Mask 1 Year Calendar Digit of Alarm Setting 0 9 3 M...

Page 582: ...is bit to check if these registers are updated done is necessary 0 RTC_SPRCTL RTC_SPR0 RTC_SPR19 updating is in progress 1 RTC_SPRCTL RTC_SPR0 RTC_SPR19 are updated done and ready to be accessed Note...

Page 583: ...MANUAL This bit controls TAMPER detect event is high level rising edge or low level falling edge 0 Low level Falling edge detection 1 High level Rising edge detection 0 SNPDEN Snoop Detection Enable...

Page 584: ...SPR8 RTC_BA 0x60 R W RTC Spare Register 8 0x0000_0000 RTC_SPR9 RTC_BA 0x64 R W RTC Spare Register 9 0x0000_0000 RTC_SPR10 RTC_BA 0x68 R W RTC Spare Register 10 0x0000_0000 RTC_SPR11 RTC_BA 0x6C R W RT...

Page 585: ...is field is used to store back up information defined by user This field will be cleared by hardware automatically once a snooper pin event is detected Before storing back up information in to RTC_SPR...

Page 586: ...stal external loading and operating temperature range The larger gain value corresponding to stronger driving capability and higher power consumption 000 L0 mode 001 L1 mode 010 L2 mode 011 L3 mode 10...

Page 587: ...to decide X32KO PF 0 I O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTOCTL control register 0 X32KO PF 0 pin I O function is controlled by GPIO module It beco...

Page 588: ...o decide X32KI PF 1 I O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL control register 0 X32KI PF 1 pin I O function is controlled by GPIO module It become...

Page 589: ...o decide PF 2 I O function is controlled by system power domain GPIO module or VBAT power domain RTC_TAMPCTL control register 0 TAMPER PF 2 I O function is controlled by GPIO module It becomes floatin...

Page 590: ...ts nCTS and RX data wake up function Supports 8 bit receiver buffer time out detection function Programmable transmitting data delay time between the last stop and the next start bit by setting DLY UA...

Page 591: ...Flow Control nCTS Wake up RX Data Wake up Auto Baud Rate Measurement STOP Bit Length 1 1 5 2 bit 1 1 5 2 bit 1 2 bit Word Length 5 6 7 8 bits Even Odd Parity Stick Bit Supported Table 6 21 NuMicro M45...

Page 592: ...3CKEN CLK_APBCLK0 19 32 768 kHz LXT Note Before clock switching both the pre selected and newly selected clock sources must be turned on and stable Figure 6 13 1 UART Clock Control Diagram UART_CLK Ir...

Page 593: ...ck is IrDA encoding control block IrDA Decode This block is IrDA decoding control block FIFO Line Control and Status Register This field is register set that including the FIFO control registers UART_...

Page 594: ...by setting the UART_FUNCSEL register The four function modes will be described in following section UART Controller Baud Rate Generator 6 13 5 1 The UART Controller includes a programmable baud rate g...

Page 595: ...IVM1 11 BRD 70 EDIVM1 15 BRD 1150 9600 BRD 142 BRD 254 EDIVM1 8 BRD 190 EDIVM1 11 BRD 142 EDIVM1 15 BRD 2302 4800 BRD 286 BRD 510 EDIVM1 8 BRD 382 EDIVM1 11 BRD 286 EDIVM1 15 BRD 4606 Table 6 24 UART...

Page 596: ...T_ALTCTL 20 19 Setting ABRDEN UART_ALTCTL 18 is to enable auto baud rate function In beginning stage the UART RX is kept at 1 Once falling edge is detected START bit is received The auto baud rate cou...

Page 597: ...IFO Control and Status 6 13 5 4 The UART Controller is built in with a 16 bytes transmitter FIFO TX_FIFO and a 16 bytes receiver FIFO RX_FIFO that reduces the number of interrupts presented to the CPU...

Page 598: ...RX Data Wake Up sleep mode HCLK UART_RX DATWKIF stable count CPU run start Figure 6 13 7 UART RX Data Wake Up UART Controller Interrupt and Status 6 13 5 6 Each UART Controller supports ten types of i...

Page 599: ...1 to BIF RLSIF FEF Write 1 to FEF RLSIF PEF Write 1 to PEF RLSIF ADDRDETF Write 1 to ADDRDETF Modem Status Interrupt MODEMINT MODEMIEN MODEMIF CTSDETF Write 1 to CTSDETF Receiver Buffer Time out Inte...

Page 600: ...acteristics by setting the UART_LINE register User can program UART_LINE register for the word length stop bit and parity bit setting The Table 6 27 list the UART word stop bit length and the parity b...

Page 601: ...the nRTS is de asserted The UART sends data out when UART detects nCTS is asserted from external device If the valid asserted nCTS is not detected the UART will not send data out APB BUS RX FIFO TX F...

Page 602: ...6 trigger level if the number of data bytes in RX FIFO is equal to or greater than RTSTRGLV UART_FIFO 19 16 the nRTS is de asserted Setting RTSACTLV UART_MODEM 9 can control the nRTS pin output is inv...

Page 603: ...ART_FUNCSEL 1 0 to 10 to enable the IrDA function The SIR specification defines a short range infrared asynchronous serial transmission mode with one start bit 8 data bits and 1 stop bit The maximum d...

Page 604: ...and TXINV UART_IRDA 5 is set to 0 IrDA SIR Operation The IrDA SIR encoder decoder provides functionality which converts between UART data stream and half duplex serial SIR interface The Figure 6 13 1...

Page 605: ...baud rate 2 Setting WLS UART_LINE 1 0 to 11 to configure the word length with 8 bits clearing PBE UART_LINE 3 bit to disable parity check and clearing NSB UART_LINE 2 bit to configure with one stop b...

Page 606: ...12 dominant bits break field and 1 recessive bit break sync delimiter Setting BRKFL UART_LINCTL 19 16 and BSL UART_LINCTL 21 20 to change the LIN break field length and break sync delimiter length Not...

Page 607: ...INIEN UART_INTEN 8 bit is set to 1 an interrupt LININT UART_INTSTS 15 will be generated The behavior of the break detection and break flag are shown in the Figure 6 13 16 LIN Bus IDLE Capture Strobe 0...

Page 608: ...set If the LINIEN UART_INTEN 8 bit is set to 1 an interrupt will be generated User can enable the frame ID parity check function by setting IDPEN UART_LINCTL 9 If only received frame ID parity is not...

Page 609: ...d sync field without frame error followed by ID data without frame error and received ID data matched PID UART_LINCTL 31 24 value The controller will enable the receiver exit from mute mode and subseq...

Page 610: ...grammed by the application during initialization TEMP_REG User can set SLVDUEN UART_LINCTL 3 to enable auto reload initial baud rate value function If the SLVDUEN UART_LINCTL 3 is set when received th...

Page 611: ...are performed in parallel Check1 Based on measurement between the first falling edge and the last falling edge of the sync field If the difference is more than 14 84 the header error flag SLVHEF UART...

Page 612: ...reception time out RS 485 Function Mode 6 13 5 10 Another alternate function of UART Controller is RS 485 function user must set UART_FUNCSEL 1 0 to 11 to enable RS 485 function and direction control...

Page 613: ...ata until an address byte is detected bit 9 1 and the address byte data will be stored in the RX FIFO If software wants to receive any data before address byte detected the flow is disables RXOFF UART...

Page 614: ...n Mode RS485AAD UART_ALTCTL 9 1 the receiver will ignore any data until an address byte is detected bit 9 1 and the address byte data matches the ADDRMV UART_ALTCTL 31 24 value The address byte data w...

Page 615: ...t voltage logic status D0 D1 D2 D3 D4 D5 D6 D7 P Start bit Stop bit TX pin output default Driver Enable nRTS pin output status of RS 485 function mode RS 485 AUD mode enabled RTSACTLV 0 RTSACTLV 1 RTS...

Page 616: ...nable RX TX nRTS Differential Bus RS 485 Transceiver UART RS 485 Controller D1 D2 D3 D4 D5 D6 D7 P Stop bit Driver Enable RTSSTS UART_MODEM 13 Note RS485AUD UART_ALTCTL 10 must be set to 1 and RTSACTL...

Page 617: ..._0000 UART_MODEM x 0 1 2 3 UARTx_BA 0x10 R W UART Modem Control Register 0x0000_0200 UART_MODEM STS x 0 1 2 3 UARTx_BA 0x14 R W UART Modem Status Register 0x0000_0110 UART_FIFOST S x 0 1 2 3 UARTx_BA...

Page 618: ...M451 May 4 2018 Page 618 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL UART_LINSTS x 0 1 UARTx_BA 0x38 R W UART LIN Status Register 0x0000_0000...

Page 619: ...28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DAT Bits Description 31 8 Reserved Reserved 7 0 DAT Receiving Transmit Buffer Write Operation B...

Page 620: ...eserved Reserved 15 RXPDMAEN RX DMA Enable Bit This bit can enable or disable RX DMA service 0 RX DMA Disabled 1 RX DMA Enabled 14 TXPDMAEN TX DMA Enable Bit This bit can enable or disable TX DMA serv...

Page 621: ...e in UART2 UART3 0 LIN bus interrupt Disabled 1 LIN bus interrupt Enabled Note This bit is used for LIN function mode 7 6 Reserved Reserved 5 BUFERRIEN Buffer Error Interrupt Enable Bit 0 Buffer error...

Page 622: ...ved Note This field is used for auto nRTS flow control 15 9 Reserved Reserved 8 RXOFF Receiver Disable The receiver is disabled or not set 1 to disable receiver 0 Receiver Enabled 1 Receiver Disabled...

Page 623: ...This bit will automatically clear at least 3 UART peripheral clock cycles 1 RXRST RX Field Software Reset When RXRST UART_FIFO 1 is set all the byte in the receiver FIFO and RX internal state machine...

Page 624: ...rity Enabled Note If PBE UART_LINE 3 and EPE UART_LINE 4 are logic 1 the parity bit is transmitted and checked as logic 0 If PBE UART_LINE 3 is 1 and EPE UART_LINE 4 is 0 then the parity bit is transm...

Page 625: ...M451 May 4 2018 Page 625 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL 00 5 bits 01 6 bits 10 7 bits 11 8 bits...

Page 626: ...te 12 10 Reserved Reserved 9 RTSACTLV nRTS Pin Active Level This bit defines the active level state of nRTS pin output 0 n RTS pin output is high level active 1 nRTS pin output is low level active Def...

Page 627: ...pin input is high level active 1 nCTS pin input is low level active Default 7 5 Reserved Reserved 4 CTSSTS nCTS Pin Status Read Only This bit mirror from nCTS pin input of voltage logic status 0 nCTS...

Page 628: ...it of the last byte has been transmitted Note This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed 27 25 Reserved Reserved 24 TXOVIF TX Overflow...

Page 629: ...of RX FIFO is read by CPU RXPTR decreases one The Maximum value shown in RXPTR is 15 When the using level of RX FIFO Buffer equal to 16 the RXFULL bit is set to 1 and RXPTR will show 0 As one byte of...

Page 630: ...ounter is overflow Note2 This bit is read only but can be cleared by writing 1 to it 1 ABRDIF Auto baud Rate Detect Interrupt Read Only 0 Auto baud rate detect function is not finished 1 Auto baud rat...

Page 631: ...MA Mode Time out Interrupt Indicator Read Only This bit is set if TOUTIEN UART_INTEN 4 and HWTOIF UART_INTSTS 20 are both set to 1 0 No Tout interrupt is generated in DMA mode 1 Tout interrupt is gene...

Page 632: ...If RLSIEN UART_INTEN 2 is enabled the RLS interrupt will be generated 0 No RLS interrupt flag is generated 1 RLS interrupt flag is generated Note1 In RS 485 function mode this field include receiver d...

Page 633: ...INT Receive Data Available Interrupt Indicator Read Only This bit is set if RDAIEN UART_INTEN 0 and RDAIF UART_INTSTS 0 are both set to 1 0 No RDA interrupt is generated 1 RDA interrupt is generated 7...

Page 634: ...t Flag Read Only This bit is set when the RX receive data have parity error frame error or break error at least one of 3 bits BIF UART_FIFOSTS 6 FEF UART_FIFOSTS 5 and PEF UART_FIFOSTS 4 is set If RLS...

Page 635: ...ut Interrupt Comparator The time out counter resets and starts counting the counting clock baud rate whenever the RX FIFO receives a new data word Once the content of time out counter is equal to that...

Page 636: ...BAUD 28 to select baud rate calculation mode The detail description is shown in Table 6 23 Note In IrDA mode must be operated in mode 0 28 BAUDM0 BAUD Rate Mode Selection Bit 0 This bit is baud rate m...

Page 637: ...ts Description 31 7 Reserved Reserved 6 RXINV IrDA Inverse Receive Input Signal 0 None inverse receiving input signal 1 Inverse receiving input signal Default 5 TXINV IrDA Inverse Transmitting Output...

Page 638: ...nput pattern shall be 0x02 10 4 bit time from Start bit to the 1st rising edge The input pattern shall be 0x08 11 8 bit time from Start bit to the 1st rising edge The input pattern shall be 0x80 Note...

Page 639: ...i drop Operation Mode NMM 0 RS 485 Normal Multi drop Operation mode NMM Disabled 1 RS 485 Normal Multi drop Operation mode NMM Enabled Note It cannot be active with RS 485_AAD operation mode 7 LINTXEN...

Page 640: ...EL x 0 1 2 3 UARTx_BA 0x30 R W UART Function Select Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved FUNC...

Page 641: ...D0 LSB first Note2 This field can be used for LIN master mode or slave mode 23 22 HSEL LIN Header Select 00 The LIN header includes break field 01 The LIN header includes break field and sync field 10...

Page 642: ...UART_LINCTL 23 22 10 or be used for enable LIN slave received frame ID parity checked Note2 This bit is only use when the operation header transmitter is in HSEL UART_LINCTL 23 22 10 8 SENDH LIN TX Se...

Page 643: ...mode the baud rate setting must be mode2 BAUDM1 UART_BAUD 29 and BAUDM0 UART_BAUD 28 must be 1 Note3 The control and interactions of this field are explained in 6 13 5 9 Slave mode with automatic res...

Page 644: ...ection function BITERREN UART_LINCTL 12 1 8 BRKDETF LIN Break Detection Flag Read Only This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software 0 LIN bre...

Page 645: ...chronization mode sync field measure time out with Automatic Resynchronization mode and LIN header reception time out 0 LIN header error not detected 1 LIN header error detected Note1 This bit is read...

Page 646: ...Supports transmitter and receiver error retry and error number limiting function Supports hardware activation sequence hardware warm reset sequence and hardware deactivation sequence process Supports...

Page 647: ...N CLKKEEP CLKKEEP Note Before clock switching both the pre selected and newly selected clock sources must be turned on and stable Figure 6 14 1 SC Clock Control Diagram 4 bit Pre scale Counter in Cloc...

Page 648: ...ts data format is composed of ten consecutive bits which is shown in Figure 6 14 3 Start Pause Start D1 Delay Between Consecutive Characters D2 D3 D4 D5 D6 D7 D8 P Figure 6 14 3 SC Data Character The...

Page 649: ...PU at the same time INITIEN SC_INTEN 8 1 5 If the TMR0 decreases the counter to 0 start from SC_RST de assert and the card does not response ATR before that time hardware will generate interrupt TMR0I...

Page 650: ...rd does not response ATR before that time hardware will generate interrupt TMR0IF SC_INTSTS 3 to CPU Undefined T6 ATR T4 T5 T4 Comment Time 00 01 10 11 81 129 161 161 483 531 563 42106 T4 Unit SC Cloc...

Page 651: ...e The SC controller also supports auto deactivation sequence when the card removal detection is enabled by setting ADAC_CDEN SC_ALTCTL 11 When hardware de asserts SC_PWR to low the controller will gen...

Page 652: ...byte is equal to 0x3F If the TS pattern is 1101_1100 it is direct convention When decoded by direct convention the conveyed byte is equal to 0x3B Software can set AUTOCEN SC_CTL 3 and then the operati...

Page 653: ...terrupt to CPU Software can also define the received retry number limitation in RXRTY SC_CTL 18 16 register The receiver retry number is up to RXRTY 1 if the number of received errors by receiver is e...

Page 654: ...e down counter is only used for hardware activation warm reset sequence to measure ATR timing The timing starts when SC_RST de assertion and ends when ATR response received or time out If the counter...

Page 655: ...ware cannot generate any interrupt to CPU The real count value will be CNTx SC_TMRDAT0 23 0 SC_TMRDAT1_2 7 0 SC_TMRDAT1_2 15 8 1 Start Start counting after TMRx_SEN SC_ALTCTL 7 5 set to 1 and the star...

Page 656: ...lowing is the program example for UART mode Program example 1 Set UARTEN SC_UARTCTL 0 bit to enter UART mode 2 Do software reset by setting RXRST SC_ALTCTL 1 and TXRST SC_ALTCTL 0 bit to ensure that a...

Page 657: ...0000 SC_ETUCTL SC_BA 0x14 R W SC ETU Control Register 0x0000_0173 SC_INTEN SC_BA 0x18 R W SC Interrupt Enable Control Register 0x0000_0000 SC_INTSTS SC_BA 0x1C R W SC Interrupt Status Register 0x0000_...

Page 658: ...ng Buffer Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DAT Bits Description 31 8 Reserved Reserved 7 0 DAT Rece...

Page 659: ...erved 26 CDLV Card Detect Level 0 When hardware detects the card detect pin SC_CD from high to low it indicates a card is detected 1 When hardware detects the card detect pin from low to high it indic...

Page 660: ...and UART adopts NSB to program the stop bit length 14 13 TMRSEL Timer Selection 00 All internal timer function Disabled 01 Internal 24 bit timer Enabled Software can configure it by setting SC_TMRCTL...

Page 661: ...setting step must be done before Answer to Reset state and the first data must be 0x3B or 0x3F After hardware received first data and stored it at buffer hardware will decided the convention and chang...

Page 662: ...er counter status of timer1 0 Timer1 is not active 1 Timer1 is active 13 ACTSTS0 Internal Timer0 Active State Read Only This bit indicates the timer counter status of timer0 0 Timer0 is not active 1 T...

Page 663: ...MRSEL SC_CTL 14 13 01 Note2 If the operation mode is not in auto reload mode SC_TMRCTL1 26 0 this bit will be auto cleared by hardware Note3 This field will be cleared by TXRST SC_ALTCTL 0 and RXRST S...

Page 664: ...nce 0 No effect 1 Deactivation sequence generator Enabled Note1 When the deactivation sequence completed this bit will be cleared automatically and the INITIF SC_INTSTS 8 will be set to 1 Note2 This f...

Page 665: ...GT SC_BA 0x0C R W SC Extend Guard Time Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 EGT Bits Description 31 8 R...

Page 666: ...RFTM 7 6 5 4 3 2 1 0 RFTM Bits Description 31 9 Reserved Reserved 8 0 RFTM SC Receiver FIFO Time out ETU Base The time out counter resets and starts counting whenever the RX buffer received a new data...

Page 667: ...2 1 0 ETURDIV Bits Description 31 16 Reserved Reserved 15 CMPEN Compensation Mode Enable Bit This bit enables clock compensation function When this bit enabled hardware will alternate between n clock...

Page 668: ...Interrupt Enable Bit This field is used for receiver buffer time out interrupt enable 0 Receiver buffer time out interrupt Disabled 1 Receiver buffer time out interrupt Enabled 8 INITIEN Initial End...

Page 669: ...US 6 frame error FEF SC_STATUS 5 parity error PEF SC_STATUS 4 receiver buffer overflow error RXOV SC_STATUS 0 transmit buffer overflow error TXOV SC_STATUS 8 receiver retry over limit error RXOVERR SC...

Page 670: ...ware wants to clear this bit software must read all receiver buffer remaining data by reading SC_DAT buffer 8 INITIF Initial End Interrupt Status Flag Read Only This field is used for activation ACTEN...

Page 671: ...R SC_STATUS 22 and transmitter retry over limit error TXOVERR SC_STATUS 30 Note This field is the status flag of BEF SC_STATUS 6 FEF SC_STATUS 5 PEF SC_STATUS 4 RXOV SC_STATUS 0 TXOV SC_STATUS 8 RXOVE...

Page 672: ...try Error Read Only This bit is set by hardware when transmitter re transmits Note1 This bit is read only but it can be cleared by writing 1 to it Note2 This bit is a flag and cannot generate any inte...

Page 673: ...d by writing 1 to it Note2 Card detect engine will start after SCEN SC_CTL 0 set 10 TXFULL Transmit Buffer Full Status Flag Read Only This bit indicates TX buffer full or not This bit is set when TX p...

Page 674: ...g RXRTYEN SC_CTL 19 hardware will not set this flag 3 Reserved Reserved 2 RXFULL Receiver Buffer Full Status Flag Read Only This bit indicates RX buffer full or not This bit is set when RX pointer is...

Page 675: ...ing is completion user can write new data to SC_PINCTL register 1 Last value is synchronizing Note This bit is read only 29 19 Reserved Reserved 18 RSTSTS SCRST Pin Signals This bit is the pin status...

Page 676: ...n to low 1 Drive SCDATOUT pin to high Note When SC is at activation warm reset or deactivation mode this bit will be changed automatically So don t fill this field when SC is in these modes 8 7 Reserv...

Page 677: ...RENCE MANUAL Read this field to get SC_PWR pin status 0 SC_PWR pin status is low 1 SC_PWR pin status is high Note When operating at activation warm reset or deactivation mode this bit will be changed...

Page 678: ...er 0 0x0000_0000 31 30 29 28 27 26 25 24 Reserved OPMODE 23 22 21 20 19 18 17 16 CNT 15 14 13 12 11 10 9 8 CNT 7 6 5 4 3 2 1 0 CNT Bits Description 31 28 Reserved Reserved 27 24 OPMODE Timer 0 Operati...

Page 679: ...31 30 29 28 27 26 25 24 Reserved OPMODE 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 CNT Bits Description 31 28 Reserved Reserved 27 24 OPMODE Timer 1 Operation Mod...

Page 680: ...31 30 29 28 27 26 25 24 Reserved OPMODE 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 CNT Bits Description 31 28 Reserved Reserved 27 24 OPMODE Timer 2 Operation Mod...

Page 681: ...effect only when PBOFF bit is 0 6 PBOFF Parity Bit Disable Control 0 Parity bit is generated or checked between the last data word bit and stop bit of the serial data 1 Parity bit is not generated tr...

Page 682: ...Description Reset Value SC_TMRDAT0 SC_BA 0x38 R SC Timer Current Data Register A 0x0000_07FF 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CNT0 15 14 13 12 11 10 9 8 CNT0 7 6 5 4 3 2 1 0 CN...

Page 683: ...Timer Current Data Register B 0x0000_7F7F 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CNT2 7 6 5 4 3 2 1 0 CNT1 Bits Description 31 16 Reserved Reserved 15...

Page 684: ...er Slave mode Bidirectional data transfer between masters and slaves Multi master bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the...

Page 685: ...Master and a Slave Data bits transfer on the SCL and SDA lines are synchronously on a byte by byte basis Each data byte is 8 bit long There is one SCL clock pulse for each data bit with the MSB being...

Page 686: ...as I 2 C ports user must set the pins function to I 2 C in advance Note Pull up resistor is needed for I 2 C operation as the SDA and SCL are open drain pins I 2 C Protocol 6 15 5 1 The Figure 6 15 3...

Page 687: ...r may send any number of bytes followed by a stop condition Instead of sending the stop condition it is also allowed to send another start condition again followed by an address and of course includin...

Page 688: ...the communication by generating a STOP signal A STOP signal usually referred to as the P bit is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH The Figure 6 15 4 shows the wavefo...

Page 689: ...is the Slave address SLA This is a 7 bit calling address followed by a Read Write R W bit The R W bit signals of the slave indicate the data transfer direction No two slaves in the system can have th...

Page 690: ...ignal to abort the data transfer or generate a Repeated START signal and start a new transfer cycle If the master as a receiving device does Not Acknowledge NACK the slave the slave releases the SDA l...

Page 691: ...transmit data from to master by setting the AA bit acknowledge pulse will be transmitted out on the 9th clock hence an interrupt is requested on both master and slave devices if interrupt is enabled...

Page 692: ...TECHNICAL REFERENCE MANUAL S I2C_DAT SLA W ACK Last Status STATUS 0x08 Updated Status STATUS 0x18 Register Control I2C_DAT SLA W STA STO SI AA 0 0 1 x Master to Slave Slave to Master Figure 6 15 9 Co...

Page 693: ...C_DAT Data ACK NAK Sr P P S STATUS 0x08 STA STO SI AA 1 0 1 x ACK STATUS 0x18 NAK STATUS 0x20 I2C_DAT SLA W STA STO SI AA 0 0 1 x ACK STATUS 0x28 NAK STATUS 0x30 I2C_DAT Data STA STO SI AA 0 0 1 x STA...

Page 694: ...AT SLA R STA STO SI AA 0 0 1 X Arbitration Lost STATUS 0x38 I2C_DAT SLA R ACK I2C_DAT SLA R STA STO SI AA 0 0 1 1 Arbitration Lost ACK STATUS 0x68 0x78 0xB0 STA STO SI AA 0 0 1 X I2 C bus will be rele...

Page 695: ...when bus free S STA STO SI AA 1 0 1 0 Switch to not addressed mode Own SLA will not be recognized Send START when bus free STA STO SI AA 0 0 1 0 Switch to not addressed mode Own SLA will not be recogn...

Page 696: ...d Slave mode but got a STOP or Repeat START the status code will be 0xA0 User could follow the action for status code 0xC8 as shown in the above figure when getting 0xA0 status Note After slave gets s...

Page 697: ...end START when bus free Switch to not addressed mode Address 0x0 will be recognized STA STO SI AA 0 0 1 0 Switch to not addressed mode Own SLA will not be recognized Become I2 C Master Become I2 C Mas...

Page 698: ...as lost arbitration can generate SCL pulses until the byte ends and must then release the bus and go into slave mode The arbitration procedure can continue until all the data is transferred This means...

Page 699: ...e a master slave and must support the SMBus host notify protocol Only one host is allowed in a system This Bus Management peripheral is based on I 2 C specification rev 2 1 Device Identification slave...

Page 700: ...ress conflicts can be resolved by dynamically assigning a new unique address to each slave device In order to provide a mechanism to isolate each device for the purpose of address assignment each devi...

Page 701: ...that it wants to talk The host processes the interrupt and simultaneously accesses all Bus Management ALERT pin s devices through the Alert Response Address 0b0001 100 Only the device s which pulled...

Page 702: ...ror Code PEC at the end of each message transfer The PEC is calculated by using the C x x 8 x 2 x 1 CRC 8 polynomial on all the message bytes including addresses and read write bits The peripheral emb...

Page 703: ...24 14 bit x TPCLK if TOCDIV4 0 CLKTO I2C_CLKTOUT 7 0 1 x 16x1024 14 bit x 4 x TPCLK if TOCDIV4 1 Bus idle detection A master can assume that the bus is free if it detects that the clock and data signa...

Page 704: ...tatus register I2C_BUSCTL bus management register I2C_BUSTCTL bus management timer control register I2C_BUSSTS bus management status register I2C_PKTSIZE TX RX byte number I2C_PKTCRC PEC value registe...

Page 705: ...h the chip s own slave address The I 2 C hardware will react if the contents of I2C_ADDRn are matched with the received slave address The I 2 C ports support the General Call function If the GC bit I2...

Page 706: ...ntroller supports multiple address recognition with four address mask registers I2C_ADDRMSKn n 0 3 When the bit in the address mask register is set to 1 it means the received corresponding address bit...

Page 707: ...is controlled by the I 2 C hardware and cannot be accessed by the CPU Serial data is shifted into I2C_DAT 7 0 on the rising edges of serial clock pulses on the SCL line When a byte has been shifted in...

Page 708: ...y hardware the SI bit is set when the I 2 C hardware requests a serial interrupt and the STO bit is cleared when a STOP condition is present on the bus The STO bit is also cleared when I2CEN 0 Once a...

Page 709: ...ease bus and to wait for a new communication The I 2 C bus cannot recognize stop condition during this action when a bus error occurs Master Mode Slave Mode STATUS Description STATUS Description 0x08...

Page 710: ...er when I 2 C is in Master Mode and it is not necessary in a Slave mode In the Slave mode I 2 C will automatically synchronize it with any clock frequency from master I 2 C device The data baud rate o...

Page 711: ...y clearing TOCEN to 0 When time out counter is enabled writing 1 to the SI flag will reset counter and re start up counting after SI is cleared If I 2 C bus hangs up it causes the I2C_STATUS and flag...

Page 712: ..._WKCTL When chip enters Power down mode other I 2 C master can wake up our chip by addressing our I 2 C device user must configure the related setting before entering Sleep mode When the chip is woken...

Page 713: ...713 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL Wake up Status Register I2C_WKSTS When system is woken up by other I 2 C master device WKIF is set to indicate this event User needs write...

Page 714: ...rt and the suspend function can be set in ALERTEN I2C_BUSCTL 4 SCTLOSTS I2C_BUSCTL 5 and SCTLOEN I2C_BUSCTL 6 The calculated PEC when the PECEN is set value is transmitted or received can be controlle...

Page 715: ...the PECEN bit I2C_BUSCTL 1 is set The I 2 C controller will calculate the PEC value of the data on the bus The I2C_PKTSIZE is used to define the data number in the bus When the counter reach the valu...

Page 716: ...f 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL I 2 C PEC VALUR Register I2C_PKTCRC The register indicates the calculated PEC value of data on the I 2 C bus The detail of information is defined...

Page 717: ...o normal operation I2C0RST 0 in the SYS_IPRST1 register 4 Set I2CEN 1 to enable I 2 C0 controller in the I2C_CTL register 5 Give I 2 C0 clock a divided register value for I 2 C clock rate in the I2C_C...

Page 718: ...TUS 0x40 NAK STATUS 0x20 I2C_DAT ROM Address Low Byte ACK STATUS 0x28 I2C_DAT ROM Address Low Byte STA STO SI AA 0 0 1 x P STATUS 0xf8 STA STO SI AA 0 1 1 x NAK STATUS 0x30 I2C_DAT Data NAK STATUS 0x5...

Page 719: ...000_0000 I2C_ADDRMSK0 I2Cn_BA 0x24 R W I2 C Slave Address Mask Register0 0x0000_0000 I2C_ADDRMSK1 I2Cn_BA 0x28 R W I2 C Slave Address Mask Register1 0x0000_0000 I2C_ADDRMSK2 I2Cn_BA 0x2C R W I2 C Slav...

Page 720: ...bus is free 4 STO I2 C STOP Control In Master mode setting STO to transmit a STOP condition to bus then I2 C controller will check the bus condition if a STOP condition is detected This bit will be c...

Page 721: ...M451 May 4 2018 Page 721 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL the SCL line 1 0 Reserved Reserved...

Page 722: ...cription Reset Value I2C_DAT I2Cn_BA 0x08 R W I2 C Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DAT Bits D...

Page 723: ...states is entered a status interrupt is requested SI 1 A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by sof...

Page 724: ...V I2Cn_BA 0x10 R W I2 C Clock Divided Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DIVIDER Bits Description 31...

Page 725: ...out Counter Enable Bit When Enabled the 14 bit time out counter will start counting when SI is clear Setting flag SI to 1 will reset counter and re start up counting after SI is cleared 0 Time Out Cou...

Page 726: ...ADDR3 I2Cn_BA 0x20 R W I2 C Slave Address Register3 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 ADDR GC Bits Descriptio...

Page 727: ...Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 ADDRMSK Reserved Bits Description 31 8 Reserved Reserved 7 1 ADDRMSK I2 C Address Mask 0 Mask Disabled the rec...

Page 728: ...tion Reset Value I2C_WKCTL I2Cn_BA 0x3C R W I2 C Wake up Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 R...

Page 729: ..._WKSTS I2Cn_BA 0x40 R W I2 C Wake up Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WKIF Bits Des...

Page 730: ...ation 0 The PEC calculation is cleared by Repeat Start function is Disabled 1 The PEC calculation is cleared by Repeat Start function is Enabled 9 TIDLE Timer Check in Idle State The BUSTOUT is used t...

Page 731: ...N Bus Management Device Default Address Enable Bit 0 Device default address Disable When the address 0 b1100001x coming and the both of BMDEN and ACKMEN are enabled the device responses NACKed 1 Devic...

Page 732: ...it 0 Indicates the I2 C state machine reset is Disable 1 Indicates the I2 C state machine reset is Enable The clock and data bus will be released to high 3 CLKTOIEN Extended Clock Time Out Interrupt E...

Page 733: ...SERIES TECHNICAL REFERENCE MANUAL 0 Indicates the bus clock low time out detection is Disabled 1 Indicates the bus clock low time out detection is Enabled bus clock is low for more than TTime out in...

Page 734: ...ime out or external clock time out occurred In bus busy the bit indicates the total clock low time out event occurred otherwise it indicates the bus idle time out event occurred Note Software can writ...

Page 735: ...n the PECEN is set 1 Indicates the transmission receive is finished when the PECEN is set Note Software can write 1 to clear this bit 0 BUSY Bus Busy Indicates that a communication is in progress on t...

Page 736: ...er Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 PLDSIZE Bits Description 31 8 Reserved Reserved 7 0 PLDSIZE Tra...

Page 737: ...cket Error Checking Byte Value Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 PECCRC Bits Description 31 8 Reserv...

Page 738: ...ister 0x0000_0005 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 BUSTO Bits Description 31 8 Reserved Reserved 7 0 BUSTO Bus Managemen...

Page 739: ...Low Timer Register 0x0000_0005 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 CLKTO Bits Description 31 8 Reserved Reserved 7 0 CLKTO...

Page 740: ...s Dual and Quad I O Transfer mode SPI1 and SPI2 controller also support I 2 S mode to connect external audio CODEC SPI2 only supported at M45xG M45xE Series 6 16 2 Features SPI Mode Up to three sets o...

Page 741: ...0 SPI0_MOSI1 SPI0_MISO1 SPI0_SS Peripheral clock Note SPI0_MOSI1 and SPI0_MISO1 are only available in 2 Bit Transfer mode or Quad I O mode Figure 6 16 1 SPI Block Diagram SPI0 APB Interface Control St...

Page 742: ...ister by peripheral clock and read out by SPI bus clock Three bit data is loaded into this buffer first and the 4 th bit data is written into the buffer after 1 bit data is read out by the SPI bus clo...

Page 743: ...ck source which can be HXT HIRC PLL out or the PCLK SPInSEL n 0 1 2 of CLK_CLKSEL2 register determines the clock source of the SPIn peripheral clock The DIVIDER SPI_CLKDIV 7 0 setting determines the d...

Page 744: ...iagram Slave Selection In Master mode the SPI controller can drive off chip slave device through the slave select output pin SPIn_SS In Slave mode the off chip master device drives the slave selection...

Page 745: ...he bit transfer sequence in a transaction If the LSB SPI_CTL 13 is set to 1 the transfer sequence is LSB first The bit 0 will be transferred firstly If the LSB SPI_CTL 13 is cleared to 0 the transfer...

Page 746: ...k 1 5 SPI clock The last transaction Figure 6 16 7 Automatic Slave Selection SSACTPOL 0 SPI_CYCLE 0x2 SPIn_SS TXEMPTY SPI_STATUS 16 SS SPI_SSCTL 0 SPIn_CLK One transaction One transaction The last tra...

Page 747: ...ction word The suspend interval is configured in SUSPITV SPI_CTL 7 4 SPIn_CLK SPIn_MISO SPIn_MOSI TX 30 TX 24 TX 23 TX 22 TX 16 RX 30 RX 24 RX 22 RX 16 MSB RX 31 Suspend Interval 1st Transaction Byte...

Page 748: ...sly For example in Master mode the even data TX Data n stored in the SPI_TX register will be transmitted through the SPI0_MOSI0 pin and the odd data TX Data n 1 stored in the SPI_TX register will be t...

Page 749: ...hen the QDIODIR bit is set to 0 the controller will read the data from the external device This function supports 8 16 24 and 32 bits of length The Dual I O mode is not supported when the Slave 3 Wire...

Page 750: ...I_CTL 20 is set to 1 the controller will send the data to external device When the QDIODIR SPI_CTL 20 is set to 0 the controller will read the data from the external device This function supports 8 16...

Page 751: ...aster input Slave output Output Output Figure 6 16 15 Bit Sequence of Quad Output Mode SPI0_SS 7 6 5 4 3 2 1 0 SPI0_CLK SPI0_MOSI0 SPI0_MISO0 QUADIOEN C 8 4 0 C 8 4 0 D 9 5 1 D 9 5 1 C 8 4 0 C 8 4 0 D...

Page 752: ...1 When the count of valid data stored in receive FIFO buffer is larger than RXTH SPI_FIFOCTL 26 24 setting RXTHIF SPI_STATUS 10 will be set to 1 Comparator Valid Data Count in Transmit FIFO Buffer TX...

Page 753: ...ons will be triggered automatically if the transmitted data are updated in time If the SPI_TX register does not be updated after all data transfer are done the transfer will stop In Master mode during...

Page 754: ...data is written to the SPI_TX register by software the data will be loaded into transmit FIFO buffer and the TXEMPTY SPI_STATUS 16 will be set to 0 The transmission will start when the slave device r...

Page 755: ...ong 3 peripheral clock cycles before the SPI bus clock is presented The other bits are held by TXUFPOL SPI_FIFOCTL 6 because there is TX underflow event The written data will be transmitted in the nex...

Page 756: ...I_STATUS 5 will be set to 1 SPIn_SS SSACTPOL 0 SPIn_CLK Slave Time out Counter Setting SLVTOIF SLVTOCNT 256 Slave Time out Counter 0 Clear by user 123456 n n 1 0 123456 n n 1 255 256 256 256 0 0 Clear...

Page 757: ...when the slave selection line goes to inactive state the SLVBEIF SPI_STATUS 6 will be set to 1 The uncompleted transaction will be dropped from TX and RX shift registers The SPI controller will issue...

Page 758: ...TUS 10 will be set to 1 The SPI controller will generate a receive FIFO interrupt to the system if the receive FIFO interrupt enable bit RXTHIEN SPI_FIFOCTL 2 is set to 1 I 2 S Mode 6 16 5 11 The SPI1...

Page 759: ...B Figure 6 16 26 MSB Justified Data Format Timing Diagram The I2S_LRCLK signal also supports PCM mode A and PCM mode B word N 1 right channel I2S_BCLK I2S_LRCLK I2S_DI I2S_DO MSB word N left channel w...

Page 760: ...8 bit data mode ORDER I2SCTL 7 0 Mono 16 bit data mode Stereo 16 bit data mode ORDER I2SCTL 7 0 N LEFT RIGHT N N 1 0 0 0 Mono 24 bit data mode Stereo 24 bit data mode 23 23 23 N LEFT RIGHT N N 1 0 31...

Page 761: ...CTL 2 1 Four SPI timing diagrams for master slave operations and the related settings are shown below SPIn_CLK SPIn_MISO SPIn_MOSI TX 6 TX 4 TX 3 TX 2 LSB TX 0 RX 6 RX 4 RX 2 LSB RX 0 MSB RX 7 RX 3 MS...

Page 762: ...ode SLVAE 1 LSB 0 DWIDTH 0x08 1 CLKPOL 0 TXNEG 1 RXNEG 0 or 2 CLKPOL 1 TXNEG 0 RXNEG 1 Figure 6 16 32 SPI Timing in Slave Mode SPIn_CLK SPIn_MOSI SPIn_MISO TX 1 TX 7 TX 0 TX 1 MSB TX 7 RX 1 RX 7 RX 1...

Page 763: ...r to control the SPI master actions 1 Configure this SPI controller as master device by setting SLAVE SPI_CTL 18 to 0 2 Force the SPI clock to low at ilde state by clearing CLKPOL SPI_CTL 3 to 0 3 Sel...

Page 764: ...I bus clock by setting TXNEG SPI_CTL 2 to 1 4 Select data latched on positive edge of SPI bus clock by clearing RXNEG SPI_CTL 1 to 0 5 Set the bit length of a transaction as 8 bit in DWIDTH bit field...

Page 765: ...Control Register 0x0000_0000 SPI_PDMACTL SPIn_BA 0x0C R W SPI PDMA Control Register 0x0000_0000 SPI_FIFOCTL SPIn_BA 0x10 R W SPI FIFO Control Register 0x4400_0000 SPI_STATUS SPIn_BA 0x14 R W SPI Stat...

Page 766: ...bled 21 DUALIOEN Dual I O Mode Enable Bit Only Supported in SPI0 0 Dual I O mode Disabled 1 Dual I O mode Enabled 20 QDIODIR Quad or Dual I O Mode Direction Control Only Supported in SPI0 0 Quad or Du...

Page 767: ...ts 7 4 SUSPITV Suspend Interval Master Only The four bits provide configurable suspend interval between two successive transmit receive transaction in a transfer The definition of the suspend interval...

Page 768: ...06 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL Note Before changing the configurations of SPI_CTL SPI_CLKDIV SPI_SSCTL and SPI_FIFOCTL registers user shall clear the SPIEN SPI_CTL 0 and confirm th...

Page 769: ...4 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DIVIDER Bits Description 31 8 Reserved Reserved 7 0 DIVIDER Clock Divider The value in this field is the frequency divider for generating the peripheral cloc...

Page 770: ...served Reserved 13 SSINAIEN Slave Select Inactive Interrupt Enable Bit 0 Slave select inactive interrupt Disabled 1 Slave select inactive interrupt Enabled 12 SSACTIEN Slave Select Active Interrupt En...

Page 771: ...to SS SPI_SSCTL 0 1 Automatic slave selection function Enabled 2 SSACTPOL Slave Selection Active Polarity This bit defines the active polarity of slave selection signal SPIn_SS 0 The slave selection...

Page 772: ...31 3 Reserved Reserved 2 PDMARST PDMA Reset 0 No effect 1 Reset the PDMA control logic of the SPI controller This bit will be automatically cleared to 0 1 RXPDMAEN Receive PDMA Enable Bit 0 Receive P...

Page 773: ...alid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0 In SPI0 RXTH is a 3 bit wide configuration in SPI1 a...

Page 774: ...FIFO Threshold Interrupt Enable Bit 0 RX FIFO threshold interrupt Disabled 1 RX FIFO threshold interrupt Enabled 1 TXRST Transmit Reset 0 No effect 1 Reset transmit FIFO pointer and transmit circuit...

Page 775: ...the reset operations of TXRST and RXRST need 3 system clock cycles 2 peripheral clock cycles User can check the status of this bit to monitor the reset function is doing or done 22 20 Reserved Reserv...

Page 776: ...ve FIFO Threshold Interrupt Flag Read Only 0 The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH 1 The valid data count within the receive FIFO buffer...

Page 777: ...upt event occurrs Note Only available in Slave mode This bit will be cleared by writing 1 to it 2 SSACTIF Slave Select Active Interrupt Flag 0 Slave select active interrupt be cleared or not occurrs 1...

Page 778: ...ata Transmit Register The data transmit registers pass through the transmitted data into the 8 4 level transmit FIFO buffer The number of valid bits depends on the setting of DWIDTH SPI_CTL 12 8 in SP...

Page 779: ...26 25 24 RX 23 22 21 20 19 18 17 16 RX 15 14 13 12 11 10 9 8 RX 7 6 5 4 3 2 1 0 RX Bits Description 31 0 RX Data Receive Register There are 8 4 level FIFO buffers in this controller The data receive...

Page 780: ...set to 1 and left channel zero cross event occurs 0 Interrupt Disabled 1 Interrupt Enabled 24 RZCIEN Right Channel Zero cross Interrupt Enable Bit Interrupt occurs if this bit is set to 1 and right ch...

Page 781: ...n_LRCLK pins are output mode and send bit clock from this chip to Audio CODEC chip In Slave mode I2Sn_BCLK and I2Sn_LRCLK pins are input mode and I2Sn_BCLK and I2Sn_LRCLK signals are received from out...

Page 782: ...ll generate bit clock in Master mode The bit clock rate F_I2SBCLK is determined by the following expression F_I2SBCLK F_I2SCLK 2x BCLKDIV 1 where F_I2SCLK is the frequency of I2 S source clock determi...

Page 783: ...of TXRST or RXRST is done 1 Doing the reset function of TXRST or RXRST Note Both the reset operations of TXRST and RXRST need 3 system clock cycles 3 peripheral clock cycles User can check the status...

Page 784: ...Master mode or over 576 peripheral clock period in Slave mode When the received FIFO buffer is read by software the time out status will be cleared automatically Note This bit will be cleared by writi...

Page 785: ...for each endpoint There are four different interrupt events in this controller They are the no event wake up device plug in or plug out event USB events like IN ACK OUT ACK etc and BUS events like sus...

Page 786: ...e scaler USBDIV CLK_CLKDIV0 7 4 to generate the proper USBD clock rate 6 17 5 Functional Description Serial Interface Engine SIE 6 17 5 1 The SIE is the front end of the device controller and handles...

Page 787: ...provides 1 interrupt vector with 4 interrupt events NEVWK VBUSDET USB and BUS The NEVWK event occurs after waking up the system from Power down mode The power mode function is defined in system power...

Page 788: ...n the buffer segmentation register before the USB function active The Buffer Control block is used to control each endpoint s effective starting address and its SRAM size is defined in the USBD_MXPLDx...

Page 789: ...tically by hardware USB_IRQ In_Rdy Data In SETUP PID Data Setup ACK PID IN PID NAK PID IN PID Data 0 1 ACK PID USB Bus Packets Setup Received Setup Handled by Firmware Set by Hardware Clear by Firmwar...

Page 790: ...Configuration Register 0x0000_0000 USBD_CFGP0 USBD_BA 0x50C R W USB Endpoint 0 Set Stall and Clear In Out Ready Control Register 0x0000_0000 USBD_BUFSEG1 USBD_BA 0x510 R W USB Endpoint 1 Buffer Segme...

Page 791: ...A 0x560 R W USB Endpoint 6 Buffer Segmentation Register 0x0000_0000 USBD_MXPLD6 USBD_BA 0x564 R W USB Endpoint 6 Maximal Payload Register 0x0000_0000 USBD_CFG6 USBD_BA 0x568 R W USB Endpoint 6 Configu...

Page 792: ...d to USBD_EPSTS register so that the USB interrupt event will not be asserted 1 IN NAK status will be updated to USBD_EPSTS register and the USB interrupt event will be asserted when the device respon...

Page 793: ...ed cleared by write 1 to USBD_INTSTS 23 or USBD_INTSTS 1 22 EPEVT6 Endpoint 6 s USB Event Status 0 No event occurred in endpoint 6 1 USB event occurred on Endpoint 6 check USBD_EPSTS 28 26 to know whi...

Page 794: ...STS 16 or USBD_INTSTS 1 15 4 Reserved Reserved 3 NEVWKIF No event wake up Interrupt Status 0 NEVWK event does not occur 1 No event wake up event occurred cleared by write 1 to USBD_INTSTS 3 2 VBDETIF...

Page 795: ...dress of a device on the USB BUS Register Offset R W Description Reset Value USBD_FADDR USBD_BA 0x008 R W USB Device Function Address Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20...

Page 796: ...rrent status of this endpoint 000 In ACK 001 In NAK 010 Out Packet Data0 ACK 011 Setup ACK 110 Out Packet Data1 ACK 111 Isochronous transfer end 28 26 EPSTS6 Endpoint 6 Status These bits are used to i...

Page 797: ...ta0 ACK 011 Setup ACK 110 Out Packet Data1 ACK 111 Isochronous transfer end 13 11 EPSTS1 Endpoint 1 Status These bits are used to indicate the current status of this endpoint 000 In ACK 001 In NAK 010...

Page 798: ...e size of the transfer from CPU to USB SRAM can be Byte only 9 PWRDN Power down PHY Transceiver Low Active M45xD M45xC Only 0 Power down related circuits of PHY transceiver 1 Turn on related circuits...

Page 799: ...e from suspend Note This bit is read only 1 SUSPEND Suspend Status 0 Bus no suspend 1 Bus idle more than 3 ms either cable is plugged off or host is sleeping Note This bit is read only 0 USBRST USB Re...

Page 800: ...alue USBD_VBUSDET USBD_BA 0x014 R USB Device VBUS Detection Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserv...

Page 801: ...7 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved STBUFSEG 7 6 5 4 3 2 1 0 STBUFSEG Reserved Bits Description 31 9 Reserved Reserved 8 3 STBUFSEG SETUP Token Buffer S...

Page 802: ...Device Drive SE0 Control Register 0x0000_0001 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SE0 Bits Description 31 1 Reserv...

Page 803: ...0000 USBD_BUFSEG5 USBD_BA 0x550 R W USB Endpoint 5 Buffer Segmentation Register 0x0000_0000 USBD_BUFSEG6 USBD_BA 0x560 R W USB Endpoint 6 Buffer Segmentation Register 0x0000_0000 USBD_BUFSEG7 USBD_BA...

Page 804: ...26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved MXPLD 7 6 5 4 3 2 1 0 MXPLD Bits Description 31 9 Reserved Reserved 8 0 MXPLD Maximal Payload Define the data length...

Page 805: ..._BA 0x568 R W USB Endpoint 6 Configuration Register 0x0000_0000 USBD_CFG7 USBD_BA 0x578 R W USB Endpoint 7 Configuration Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 R...

Page 806: ...TECHNICAL REFERENCE MANUAL This bit is used to set the endpoint as Isochronous endpoint no handshaking 0 No Isochronous endpoint 1 Isochronous endpoint 3 0 EPNUM Endpoint Number These bits are used t...

Page 807: ...t 5 Set Stall and Clear In Out Ready Control Register 0x0000_0000 USBD_CFGP6 USBD_BA 0x56C R W USB Endpoint 6 Set Stall and Clear In Out Ready Control Register 0x0000_0000 USBD_CFGP7 USBD_BA 0x57C R W...

Page 808: ...ry and USB bus port power control and port over current detection The USBH is responsible for detecting the connect and disconnect of USB devices managing data transfer collecting status and activity...

Page 809: ...FERENCE MANUAL 6 18 3 Block Diagram SIE AHB Bus AHB Interface Wrapper List Processor Bus Master Control Register Data Buffer SIE Frame Management Port Control Interrupts Root Hub Control Clock Generat...

Page 810: ...red by the USB specification and the OpenHCI specification These tasks are 1 Management of the OpenHCI frame specific Operational Registers 2 Operation of the Largest Data Packet Counter 3 Performing...

Page 811: ...18 Page 811 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL The Root Hub is a collection of ports that are individually controlled and a hub that maintains control status over functions common...

Page 812: ...ROL HEADED USBH_BA 0x020 R W Host Controller Control Head ED Register 0x0000_0000 HCCONTROL CURRENTED USBH_BA 0x024 R W Host Controller Control Current ED Register 0x0000_0000 HCBULKHEA DED USBH_BA 0x...

Page 813: ...NCE MANUAL HCRHPORTS TATUS1 USBH_BA 0x054 R W Host Controller Root Hub Port Status 1 0x0000_0000 HCPHYCONT ROL USBH_BA 0x200 R W Host Controller PHY Control Regsiter 0x0000_0000 HCMISCCONT ROL USBH_BA...

Page 814: ...Value HCREVISION USBH_BA 0x000 R Host Controller Revision Register 0x0000_0110 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 REV Bits...

Page 815: ...ng from a downstream port States are 00 USBRESET 01 USBRESUME 10 USBOPERATIONAL 11 USBSUSPEND 5 BLE Bulk List Enable Bit 0 Processing of the Bulk list after next SOF Start Of Frame Disabled 1 Processi...

Page 816: ...as to set both PLE and IE HcControl 3 high 1 0 CBSR Control Bulk Service Ratio This specifies the service ratio between Control and Bulk EDs Before processing any of the non periodic lists HC must com...

Page 817: ...y either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list 0 No active TD found or Host Controller begins to process the head...

Page 818: ...anged 5 FNO Frame Number Overflow This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1 0 The bit 15 of Frame Number didn t change 1 The bit 15 of Frame Number changes from 1...

Page 819: ...819 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL 0 SO Scheduling Overrun Set when the List Processor determines a Schedule Overrun has occurred 0 Schedule Overrun didn t occur 1 Schedule O...

Page 820: ...atus 3 SF HcInterruptStatus 2 WDH HcInterruptStatus 1 or SO HcInterruptStatus 0 Enabled if the corresponding bit in HcInterruptEnable is high Read Operation 0 Interrupt generation due to RHSC HcInterr...

Page 821: ...ruptStatus 3 Enabled 2 SF Start of Frame Enable Bit Write Operation 0 No effect 1 Interrupt generation due to SF HcInterruptStatus 2 Enabled Read Operation 0 Interrupt generation due to SF HcInterrupt...

Page 822: ...pt generation due to RHSC HcInterruptStatus 6 FNO HcInterruptStatus 5 RD HcInterruptStatus 3 SF HcInterruptStatus 2 WDH HcInterruptStatus 1 or SO HcInterruptStatus 0 Disabled even if the corresponding...

Page 823: ...abled Read Operation 0 Interrupt generation due to SF HcInterruptStatus 2 Disabled 1 Interrupt generation due to SF HcInterruptStatus 2 Enabled 1 WDH Write Back Done Head Disable Bit Write Operation 0...

Page 824: ...eset Value HCHCCA USBH_BA 0x018 R W Host Controller Communication Area Register 0x0000_0000 31 30 29 28 27 26 25 24 HCCA 23 22 21 20 19 18 17 16 HCCA 15 14 13 12 11 10 9 8 HCCA 7 6 5 4 3 2 1 0 Reserve...

Page 825: ...Value HCPERIODCUR RENTED USBH_BA 0x01 C R W Host Controller Period Current ED Register 0x0000_0000 31 30 29 28 27 26 25 24 PCED 23 22 21 20 19 18 17 16 PCED 15 14 13 12 11 10 9 8 PCED 7 6 5 4 3 2 1 0...

Page 826: ...Reset Value HCCONTROLHE ADED USBH_BA 0x020 R W Host Controller Control Head ED Register 0x0000_0000 31 30 29 28 27 26 25 24 CHED 23 22 21 20 19 18 17 16 CHED 15 14 13 12 11 10 9 8 CHED 7 6 5 4 3 2 1 0...

Page 827: ...alue HCCONTROLCU RRENTED USBH_BA 0x024 R W Host Controller Control Current ED Register 0x0000_0000 31 30 29 28 27 26 25 24 CCED 23 22 21 20 19 18 17 16 CCED 15 14 13 12 11 10 9 8 CCED 7 6 5 4 3 2 1 0...

Page 828: ...Reset Value HCBULKHEADE D USBH_BA 0x028 R W Host Controller Bulk Head ED Register 0x0000_0000 31 30 29 28 27 26 25 24 BHED 23 22 21 20 19 18 17 16 BHED 15 14 13 12 11 10 9 8 BHED 7 6 5 4 3 2 1 0 BHED...

Page 829: ...ion Reset Value HCBULKCURRE NTED USBH_BA 0x02 C R W Host Controller Bulk Current ED Register 0x0000_0000 31 30 29 28 27 26 25 24 BCED 23 22 21 20 19 18 17 16 BCED 15 14 13 12 11 10 9 8 BCED 7 6 5 4 3...

Page 830: ...t Value HCDONEHEAD USBH_BA 0x030 R W Host Controller Done Head Register 0x0000_0000 31 30 29 28 27 26 25 24 DH 23 22 21 20 19 18 17 16 DH 15 14 13 12 11 10 9 8 DH 7 6 5 4 3 2 1 0 DH Reserved Bits Desc...

Page 831: ...tion 31 FIT Frame Interval Toggle This bit is toggled by Host Controller Driver when it loads a new value into FI HcFmInterval 13 0 0 Host Controller Driver didn t load new value into FI HcFmInterval...

Page 832: ...6 Reserved 15 14 13 12 11 10 9 8 Reserved FR 7 6 5 4 3 2 1 0 FR Bits Description 31 FRT Frame Remaining Toggle This bit is loaded from the FIT HcFmInterval 31 whenever FR HcFmRemaining 13 0 reaches 0...

Page 833: ...USBH_BA 0x03 C R Host Controller Frame Number Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 FN 7 6 5 4 3 2 1 0 FN Bits Description 31 16...

Page 834: ...DICST ART USBH_BA 0x040 R W Host Controller Periodic Start Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved PS 7 6 5 4 3 2 1 0 PS B...

Page 835: ...28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved LST 7 6 5 4 3 2 1 0 LST Bits Description 31 12 Reserved Reserved 11 0 LST Low speed Threshold This field contain...

Page 836: ...ion This bit describes how the over current status for the Root Hub ports reported 0 Over current status is reported 1 Over current status is not reported 11 OCPM over Current Protection Mode This bit...

Page 837: ...12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Description 31 16 PPCM Port Power Control Mask Global power switching This field is only valid if PowerSwitchingMode is set individual port switchi...

Page 838: ...HcRhStatus 15 31 18 Reserved Reserved 17 OCIC over Current Indicator Change This bit is set by hardware when a change has occurred in OCI HcRhStatus 1 Write 1 to clear this bit to zero 0 OCI HcRhStatu...

Page 839: ...of the over current status pin This field is only valid if NOCP HcRhDesA 12 and OCPM HcRhDesA 11 are cleared 0 No over current condition 1 Over current condition 0 LPS Clear Global Power In global pow...

Page 840: ...l has completed Write 1 to clear this bit to zero 0 Port reset is not complete 1 Port reset is complete 19 OCIC Port over Current Indicator Change This bit is set when POCI HcRhPortStatus1 3 changes W...

Page 841: ...peed device 1 Low speed device 8 PPS Port Power Status This bit reflects the power state of the port regardless of the power switching mode Write Operation 0 No effect 1 Port Power Enabled Read Operat...

Page 842: ...t 1 Set port suspend Read Operation 0 Port is not suspended 1 Port is selectively suspended 1 PES Port Enable Status Write Operation 0 No effect 1 Set port enable Read Operation 0 Port Disabled 1 Port...

Page 843: ...4 Reserved STBYEN Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Description 31 28 Reserved Reserved 27 STBYEN USB Transceiver Standby Enable Bi...

Page 844: ...sabled the USB host controller will not recognize any event of USB bus Set this bit high the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operatio...

Page 845: ...upport both full speed and low speed transfer In Device only mode USB frame acts as USB device USB frame only supports full speed transfer In ID dependent mode USB frame can be USB Host or USB device...

Page 846: ...Description The role of USB frame depends on the setting of USBROLE SYS_USBPHY 1 0 and USB_ID pin status The USBROLE configuration has precedence over USB_ID pin status User can configure the OTG con...

Page 847: ...evice 2 0 FS Controller OTG State Machine APB Figure 6 19 2 USB Device Mode USB Host Mode When USBROLE SYS_USBPHY 1 0 is set to 1 USB frame acts as USB host USB device function is not available USB PH...

Page 848: ...s to connect to A device 3 A device recognizes USB bus power request through checking SRPDETIF OTG_INTSTS 13 4 A device starts to drive VBUS by setting BUSREG OTG_CTL 1 to 1 once SRPDETIF OTG_INTSTS 1...

Page 849: ...able command successfully user enables B peripheral HNP function by setting HNPREQEN OTG_CTL 2 to 1 2 User sets BUSREG OTG_CTL 1 to 1 after detecting USB bus in J state USB_D high and USB_D low Then U...

Page 850: ...This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state When USB frame as B device set this bit after the OTG A device successfully sends a SetFeatu...

Page 851: ...TG_CTL 0 bit is set IDSTS OTG_STATUS 1 changed 0 Not launch VBUS in OTG A device or not request SRP in OTG B device 1 Launch VBUS in OTG A device or request SRP in OTG B device 0 VBUSDROP Drop VBUS Co...

Page 852: ...S power switch valid status is high 1 The polarity of off chip USB VBUS power switch valid status is low 4 VBENPOL Off chip USB VBUS Power Switch Enable Polarity The OTG controller will enable off chi...

Page 853: ...high to low or from low to high a interrupt will be asserted 0 Interrupt Disabled 1 Interrupt Enabled 10 VBCHGIEN VBUSVLD Status Changed Interrupt Enable Bit If this bit is set to 1 and VBUSVLD OTG_S...

Page 854: ...igh a interrupt will be asserted 0 Interrupt Disabled 1 Interrupt Enabled 4 GOIDLEIEN OTG Device Goes to IDLE State Interrupt Enable Bit 0 Interrupt Disabled 1 Interrupt Enabled Note Going to idle sta...

Page 855: ...State Change Interrupt Status 0 SESSEND OTG_STATUS 2 not toggled 1 SESSEND OTG_STATUS 2 from high to low or from low to high Note Write 1 to clear this flag 10 VBCHGIF VBUSVLD State Change Interrupt...

Page 856: ...to B device before specified interval expires 1 A device does not connect to B device before specified interval expires Note Write 1 to clear this flag 2 SRPFIF SRP Fail Interrupt Status After initiat...

Page 857: ...D A device Session Valid Status 0 A device session is not valid 1 A device session is valid 3 BVLD B device Session Valid Status 0 B device session is not valid 1 B device session is valid 2 SESSEND S...

Page 858: ...ests as well as the generation of the module interrupt The register set of the C_CAN can be accessed directly by the software through the module interface These registers are used to control configure...

Page 859: ...CAN_TX CAN_RX CAN_WAKEUP 16 bit APB Interface CAN_INT Interrupt C_CAN Figure 6 20 1 CAN Peripheral Block Diagram 6 20 5 Functional Description Software Initialization 6 20 5 1 The software initializa...

Page 860: ...tency in case of concurrent accesses Messages to be transmitted are updated by the application software If a permanent Message Object arbitration and control bits are set during configuration exists f...

Page 861: ...valid data frames and valid remote frames but it sends only recessive bits on the CAN bus and it cannot start a transmission If the CAN Core is required to send a dominant bit ACK bit Error Frames th...

Page 862: ...N system connected to the CAN_TX and CAN_RX pins In this mode the CAN_RX pin is disconnected from the CAN Core and the CAN_TX pin is held recessive The Figure 6 20 4 shows the connection of signals CA...

Page 863: ...output mode for the CAN_TX pin is selected by programming the Tx1 CAN_TEST 6 and Tx0 CAN_TEST 5 bits The three test functions of the CAN_TX pin interfere with all CAN protocol functions CAN_TX must b...

Page 864: ...e initiates a data transfer between the IFn Registers and Message RAM the Message Handler sets the Busy bit CAN_IFn_CREQ 15 to 1 After the transfer has completed the Busy bit is again cleared see the...

Page 865: ...ssage RAM the MsgVal bit CAN_IFn_ARB2 15 and TxRqst bits CAN_TXREQ1 2 are evaluated The valid Message Object with the highest priority pending transmission request is loaded into the shift register by...

Page 866: ...The NewDat bit CAN_IFn_MCON 15 is set to indicate that new data not yet seen by the software has been received The application software should reset NewDat bit when the Message Object has been read I...

Page 867: ...a Register values DLC3 0 CAN_IFn_MCON 3 0 Data 0 7 are provided by the application TxRqst and RmtEn may not be set before the data is valid The Mask Registers Msk28 0 UMask MXtd and MDir bits may be u...

Page 868: ...it CAN_IFn_ARB2 13 should not be masked in typical applications Handling Received Messages 6 20 7 10 The application software may read a received message any time through the IFn Interface registers T...

Page 869: ...Message Object is set By setting NewDat while EoB CAN_IFn_MCON 7 is zero the Message Object is locked for further write access by the Message Handler until the application software has written the Ne...

Page 870: ...onological order An interrupt remains pending until the application software has cleared it The Status Interrupt has the highest priority Among the message interrupts interrupt priority of the Message...

Page 871: ...imultaneously try to transmit a frame a misplaced sample point may cause one of the transmitters to become error passive The analysis of such sporadic errors requires a detailed knowledge of the CAN b...

Page 872: ...rent bit time configurations but for the proper function of the CAN network the physical delay time and the oscillator s tolerance range have to be considered Propagation Time Segment 6 20 7 17 This p...

Page 873: ...happen that node A samples a recessive bit instead of a dominant bit resulting in a bit error and the destruction of the current frame by an error flag The error occurs only when two nodes arbitrate f...

Page 874: ...nnot compensate the phase error completely an error phase error SJW remains Only one synchronization may be done between two Sample Points The Synchronizations maintain a minimum distance between edge...

Page 875: ...Point is the same as it would have been from an Sync_Seg to the Sample Point if no edge had occurred As in the previous example the magnitude of this early edge s phase error is less than SJW so it is...

Page 876: ...protocol update to version 2 0 A and B had no influence on the oscillator tolerance The tolerance range df for an oscillator frequency fosc around the nominal frequency fnom is 1 df fnom fosc 1 df fn...

Page 877: ...Prop_Seg Phase_Seg1 Phase_Seg2 tq Baudrate_Prescaler APB Clock Configuration BRP Bit Timing Logic Received_Data Transmit_Data Sample_Point Sample_Bit Sync_Mode Bit_to_send Bus_Off Bit Stream Processo...

Page 878: ...h as well as a maximum node delay has to be defined for expandible CAN bus systems The resulting time for Prop_Seg is converted into time quanta rounded up to the nearest integer multiple of tq The Sy...

Page 879: ...river 50 ns delay of receiver circuit 30 ns delay of bus line 40m 220 ns tProp 600 ns 6 tq tSJW 100 ns 1 tq tTSeg1 700 ns tProp tSJW tTSeg2 200 ns Information Processing Time 1 tq tSync Seg 100 ns 1 t...

Page 880: ...bus driver 200 ns delay of receiver circuit 80 ns delay of bus line 40m 220 ns tProp 1 us 1 tq tSJW 4 us 4 tq tTSeg1 5 us tProp tSJW tTSeg2 4 us Information Processing Time 3 tq tSync Seg 1 us 1 tq b...

Page 881: ...k Registers 0x0000_0000 CAN_IFn_MASK1 n 1 2 CAN_BA 0x28 0x60 n 1 R W IFn Mask 1 Registers 0x0000_FFFF CAN_IFn_MASK2 n 1 2 CAN_BA 0x2C 0x60 n 1 R W IFn Mask 2 Registers 0x0000_FFFF CAN_IFn_ARB1 n 1 2 C...

Page 882: ...essage Valid Register 2 0x0000_0000 CAN_WU_EN CAN_BA 0x168 R W Wake up Enable Control Register 0x0000_0000 CAN_WU_STATUS CAN_BA 0x16C R W Wake up Status Register 0x0000_0000 Note 1 0x00 0br0000000 whe...

Page 883: ...is set to recessive HIGH The value 0x0001 Init 1 in the CAN Control Register enables the software initialization The C_CAN does not influence the CAN bus until the application software resets the Ini...

Page 884: ...EPass RxOk TxOk LEC 08h CAN_ERR RP REC6 0 TEC7 0 0Ch CAN_BTIME Res TSeg2 TSeg1 SJW BRP 10h CAN_IIDR IntId15 8 IntId7 0 14h CAN_TEST Reserved Rx Tx1 Tx0 LBack Silent Basic Reserved 18h CAN_BRPE Reserv...

Page 885: ...N_IF1_DAT_ A2 Data 3 Data 2 44h CAN_IF1_DAT_ B1 Data 5 Data 4 48h CAN_IF1_DAT_ B2 Data 7 Data 6 80h CAN_IF2_CREQ Busy Reserved Message Number 84h CAN_IF2_CMAS K Reserved WR RD Mask Arb Control ClrIntP...

Page 886: ...104h CAN_TXREQ2 TxRqst32 17 120h CAN_NDAT1 NewDat16 1 124h CAN_NDAT2 NewDat32 17 140h CAN_IPND1 IntPnd16 1 144h CAN_IPND2 IntPnd32 17 160h CAN_MVLD1 MsgVal16 1 164h CAN_MVLD2 MsgVal32 17 168h CAN_WU_...

Page 887: ...llocates an address space of 256 bytes The registers are organized as 16 bit registers The two sets of interface registers IF1 and IF2 control the software access to the Message RAM They buffer the da...

Page 888: ...TIME allowed while Init bit CAN_CON 0 1 5 DAR Automatic Re transmission Disable Bit 0 Automatic Retransmission of disturbed messages Enabled 1 Automatic Retransmission Disabled 4 Reserved Reserved 3 E...

Page 889: ...the CPU the device will then wait for 129 occurrences of Bus Idle 129 11 consecutive recessive bits before resuming normal operations At the end of the bus off recovery sequence the Error Management C...

Page 890: ...ned in the CAN Specification 4 RxOK Received a Message Successfully 0 No message has been successfully received since this bit was last reset by the CPU This bit is never reset by the CAN Core 1 A mes...

Page 891: ...ecovery this status is set each time a sequence of 11 recessive bits has been monitored This enables the CPU to monitor the proceedings of the bus off recovery sequence indicating the bus is not stuck...

Page 892: ...ved 15 14 13 12 11 10 9 8 RP REC 7 6 5 4 3 2 1 0 TEC Bits Description 31 16 Reserved Reserved 15 RP Receive Error Passive 0 The Receive Error Counter is below the error passive level 1 The Receive Err...

Page 893: ...or TSeg1 are 1 15 The actual interpretation by the hardware of this value is such that one more than the value programmed is used 7 6 SJW Re Synchronization Jump Width 0x0 0x3 Valid programmed values...

Page 894: ...ins pending until the application software has cleared it If IntId is different from 0x0000 and IE CAN_CON 1 is set the IRQ interrupt signal to the EIC is active The interrupt remains active until Int...

Page 895: ...Tx Control of CAN_TX Pin 00 Reset value CAN_TX pin is controlled by the CAN Core 01 Sample Point can be monitored at CAN_TX pin 10 CAN_TX pin drives a dominant 0 value 11 CAN_TX pin drives a recessive...

Page 896: ...0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved BRPE Bits Description 31 4 Reserved Reserved 3 0 BRPE BRPE Baud R...

Page 897: ...er sets Each set of Interface Registers consists of Message Buffer Registers controlled by their own Command Registers The Command Mask Register specifies the direction of the data transfer and which...

Page 898: ...Message Number Message Number 0x01 0x20 Valid Message Number the Message Object in the Message RAM is selected for data transfer 0x00 Not a valid Message Number interpreted as 0x20 0x21 0x3F Not a val...

Page 899: ...data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers 1 Write Transfer data from the selected Message Buffer Registers to the Message Objec...

Page 900: ...Message Control Register will be ignored Access New Data Bit when Read Operation 0 NewDat bit remains unchanged 1 Clear NewDat bit in the Message Object Note A read access to a Message Object can be...

Page 901: ...ask 1 Registers 0x0000_FFFF 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Msk 15 8 7 6 5 4 3 2 1 0 Msk 7 0 Bits Description 31 16 Reserved Reserved 15 0 Msk 1...

Page 902: ...ifier bit IDE is used for acceptance filtering Note When 11 bit standard Identifiers are used for a Message Object the identifiers of received Data Frames are written into bits ID28 to ID18 CAN_IFn_AR...

Page 903: ...CAN_IFn_ARB1 n 1 2 CAN_BA 0x30 0x60 n 1 R W IFn Arbitration 1 Registers 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 ID 15 8 7 6 5 4 3 2 1 0 ID 7...

Page 904: ...ore the identifier Id28 0 CAN_IFn_ARB1 2 the control bits Xtd CAN_IFn_ARB2 14 Dir CAN_IFn_ARB2 13 or the Data Length Code DLC3 0 CAN_IFn_MCON 3 0 are modified or if the Messages Object is no longer re...

Page 905: ...bit was reset by the CPU 1 The Message Handler stored a new message into this object when NewDat was still set the CPU has lost a message 13 IntPnd Interrupt Pending 0 This message object is not the s...

Page 906: ...Frame has 0 8 data bytes 9 15 Data Frame has 8 data bytes Note The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other n...

Page 907: ...n_DAT_A1 n 1 2 CAN_BA 0x3C 0x60 n 1 R W IFn Data A1 Registers Register Map Note 3 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Data 1 7 6 5 4 3 2...

Page 908: ...IFn_DAT_A2 n 1 2 CAN_BA 0x40 0x60 n 1 R W IFn Data A2 Registers Register Map Note 3 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Data 3 7 6 5 4 3...

Page 909: ...IFn_DAT_B1 n 1 2 CAN_BA 0x44 0x60 n 1 R W IFn Data B1 Registers Register Map Note 3 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Data 5 7 6 5 4 3...

Page 910: ...0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Data 7 7 6 5 4 3 2 1 0 Data 6 Bits Description 31 16 Reserved Reserved 15 8 Data 7 Data Byte 7 8th d...

Page 911: ...B2 14 and Dir CAN_IFn_ARB2 13 are used to define the identifier and type of outgoing messages and are used together with the mask registers Msk28 0 CAN_IFn_MASK1 2 MXtd CAN_IFn_MASK2 15 and MDir CAN_I...

Page 912: ...face Registers or by the Message Handler after reception of a Remote Frame or after a successful transmission Register Offset R W Description Reset Value CAN_TXREQ1 CAN_BA 0x100 R Transmission Request...

Page 913: ...egister 2 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 TxRqst32 25 7 6 5 4 3 2 1 0 TxRqst24 17 Bits Description 31 16 Reserved Reserved 15 0 TxRq...

Page 914: ...Frame or after a successful transmission Register Offset R W Description Reset Value CAN_NDAT1 CAN_BA 0x120 R New Data Register 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16...

Page 915: ...7 16 Reserved 15 14 13 12 11 10 9 8 NewData32 25 7 6 5 4 3 2 1 0 NewData24 17 Bits Description 31 16 Reserved Reserved 15 0 NewData32 17 New Data Bits 32 17 of All Message Objects 0 No new data has be...

Page 916: ...sters or by the Message Handler after reception or after a successful transmission of a frame This will also affect the value of IntId in the Interrupt Register Register Offset R W Description Reset V...

Page 917: ...Interrupt Pending Register 2 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 IntPnd32 25 7 6 5 4 3 2 1 0 IntPnd24 17 Bits Description 31 16 Reserve...

Page 918: ...Register Offset R W Description Reset Value CAN_MVLD1 CAN_BA 0x160 R Message Valid Register 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 MsgVa...

Page 919: ...21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 MsgVal32 25 7 6 5 4 3 2 1 0 MsgVal24 17 Bits Description 31 16 Reserved Reserved 15 0 MsgVal32 17 Message Valid Bits 32 17 of All Message Objects Read...

Page 920: ...R W Wake up Enable Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WAKUP_EN Bits Description 31...

Page 921: ...CAN_WU_STATUS CAN_BA 0x16C R W Wake up Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WAKUP_STS...

Page 922: ...seed value Supports programmable order reverse setting for input data and CRC checksum Supports programmable 1 s complement setting for input data and CRC checksum Supports 8 16 32 bit of data width 8...

Page 923: ...gram sequence example 1 Enable CRC generator by setting CRCEN CRC_CTL 0 CRC Channel Enable Control 2 Initial setting for CRC calculation Configure 1 s complement for CRC checksum by setting CHKSFMT CR...

Page 924: ...oth read and write Register Offset R W Description Reset Value CRC Base Address CRC_BA 0x4003_1000 CRC_CTL CRC_BA 0x00 R W CRC Control Register 0x2000_0000 CRC_DAT CRC_BA 0x04 R W CRC Write Data Regis...

Page 925: ...mode 29 28 DATLEN CPU Write Data Length This field indicates the write data length 00 Data length is 8 bit mode 01 Data length is 16 bit mode 1x Data length is 32 bit mode Note When the write data len...

Page 926: ...used to enable the bit order reverse function for write data value in CRC_DAT register 0 Bit order reversed for CRC write data in Disabled 1 Bit order reversed for CRC write data in Enabled per byte N...

Page 927: ...DATA 23 22 21 20 19 18 17 16 DATA 15 14 13 12 11 10 9 8 DATA 7 6 5 4 3 2 1 0 DATA Bits Description 31 0 DATA CRC Write Data Bits User can write data directly by CPU mode or use PDMA function to write...

Page 928: ...r CRC_SEED Register Offset R W Description Reset Value CRC_SEED CRC_BA 0x08 R W CRC Seed Register 0xFFFF_FFFF 31 30 29 28 27 26 25 24 SEED 23 22 21 20 19 18 17 16 SEED 15 14 13 12 11 10 9 8 SEED 7 6 5...

Page 929: ...ster Offset R W Description Reset Value CRC_CHECKSUM CRC_BA 0x0C R CRC Checksum Register 0x0000_0000 31 30 29 28 27 26 25 24 CHECKSUM 23 22 21 20 19 18 17 16 CHECKSUM 15 14 13 12 11 10 9 8 CHECKSUM 7...

Page 930: ...t channels 3 internal channels they are band gap voltage VBG temperature sensor VTEMP and Battery power VBAT Four ADC interrupts ADINT0 3 with individual interrupt vector addresses Maximum ADC clock f...

Page 931: ...le Module 0 Result Register EADC_DAT0 Control Register EADC_SCTL0 VREFCTL SYS_VREFCTL 4 0 Figure 6 22 1 ADC Converter Block Diagram 6 22 4 Basic Configuration Table 4 1 lists M451 GPIO Multi function...

Page 932: ...le module 4 15 are shows as Figure 6 22 2 Disable hardware Trigger 19 to 1 MUX TRGSEL EADC_SCTL0 20 16 ADC STADC pin signal ADC Sample and Priority control Logic Sample Module 0 Result Register DAT0 C...

Page 933: ...overflow pulse 4h Timer1 overflow pulse Timer2 overflow pulse Timer3 overflow pulse 6h 7h 8h 10h 11h 12h 13h PWM0TG0 PWM0TG1 PWM0TG2 PWM0TG3 PWM0TG4 PWM0TG5 PWM1TG0 PWM1TG1 PWM1TG2 PWM1TG3 PWM1TG4 PWM...

Page 934: ...CDIV CLK_CLKDIV0 23 16 PCLK1 Figure 6 22 5 EADC Clock Control ADC Software Trigger 6 22 5 2 When a ADC conversion is performed for specified single channel on the sample module the operations are as f...

Page 935: ...6 Example ADC Conversion Timing Diagram n 0 18 ADC Conversion Priority 6 22 5 3 There is a priority group converter for determining the conversion order when multiple sample module trigger flags are...

Page 936: ...The ADINT0 ADINT1 interrupt pulses are generated whenever the specific sample module A D EOC pulse is generated It also can be the sample module conversion trigger sources and user can use it to do t...

Page 937: ...15 to 0x01 is to select external trigger input from the STADC pin User can set EXTFEN EADC_SCTLn 5 n 0 15 and EXTREN EADC_SCTLn 4 n 0 15 to enable pin STADC trigger condition is falling or rising edg...

Page 938: ...riggered ADC start conversion Delay time Delay time Starts A D converting Starts A D converting Synchronized with PWM rising edge Synchronized with PWM falling edge Starts A D converting Synchronized...

Page 939: ...12 Conversion Start Delay Timing Diagram A D Extend Sampling Time 6 22 5 8 When A D operation at high ADC clock rate the sampling time of analog input voltage may not enough if the analog channel has...

Page 940: ...ults from A D conversion module as shown in theFigure 6 22 14 User can select which sample module result to be monitored by set CMPSPL EADC_CMPn 7 3 n 0 3 and CMPCOND EADC_CMPn 2 n 0 3 is used to chec...

Page 941: ...e ADC controller supports analog differential mode If user enable DIFFEN EADC_CTL 8 the differential mode will enable Differential analog input voltage Vdiff Vplus Vminus where Vplus is the analog inp...

Page 942: ...ead EADC_CURDAT to get result The EADC_CURDAT register is a shadow register of highest priority EADC_DAT register The lower number sample module is higher priority After PDMA read EADC_CURDAT register...

Page 943: ...R A D Data Register 10 for Sample Module 10 0x0000_0000 EADC_DAT11 EADC_BA 0x2C R A D Data Register 11 for Sample Module 11 0x0000_0000 EADC_DAT12 EADC_BA 0x30 R A D Data Register 12 for Sample Module...

Page 944: ...Module 13 Control Register 0x0000_0000 EADC_SCTL14 EADC_BA 0xB8 R W A D Sample Module 14 Control Register 0x0000_0000 EADC_SCTL15 EADC_BA 0xBC R W A D Sample Module 15 Control Register 0x0000_0000 EA...

Page 945: ...0xFC R A D Status Register 3 0x0000_001F EADC_DDAT0 EADC_BA 0x100 R A D Double Data Register 0 for Sample Module 0 0x0000_0000 EADC_DDAT1 EADC_BA 0x104 R A D Double Data Register 1 for Sample Module 1...

Page 946: ...EADC_DAT8 EADC_BA 0x20 R A D Data Register 8 for Sample Module 8 0x0000_0000 EADC_DAT9 EADC_BA 0x24 R A D Data Register 9 for Sample Module 9 0x0000_0000 EADC_DAT10 EADC_BA 0x28 R A D Data Register 10...

Page 947: ...not been read before new conversion result is loaded to this register OV is set to 1 0 Data in RESULT 11 0 is recent conversion result 1 Data in RESULT 11 0 is overwrite Note It is cleared by hardware...

Page 948: ...ter 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved CURDAT 15 14 13 12 11 10 9 8 CURDAT 7 6 5 4 3 2 1 0 CURDAT Bits Description 31 18 Reserved Reserved 17 0 CURDAT ADC PD...

Page 949: ...ADC clock sampling time 100 5 ADC clock sampling time 101 6 ADC clock sampling time 110 7 ADC clock sampling time 111 8 ADC clock sampling time 15 12 Reserved Reserved 11 PDMAEN PDMA Transfer Enable...

Page 950: ...ic Sample Module A D ADINT1 Interrupt Enable Bit The A D converter generates a conversion end ADIF1 EADC_STATUS2 1 upon the end of specific sample module A D conversion If ADCIEN1 bit is set then conv...

Page 951: ...18 17 16 Reserved SWTRG 15 14 13 12 11 10 9 8 SWTRG 7 6 5 4 3 2 1 0 SWTRG Bits Description 31 19 Reserved Reserved 18 0 SWTRG A D Sample Module 0 18 Software Force to Start ADC Conversion 0 No effect...

Page 952: ...11 10 9 8 STPF 7 6 5 4 3 2 1 0 STPF Bits Description 31 19 Reserved Reserved 18 0 STPF A D Sample Module 0 18 Start of Conversion Pending Flag Read 0 There is no pending conversion for sample module...

Page 953: ...e Start of Conversion Overrun Flag Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved SPOVF 15 14 13 12 11 10 9 8 SPOVF 7 6 5 4 3 2 1 0 SPOVF Bits Description 31 19...

Page 954: ...BMEN INTPOS Reserved TRGSEL 15 14 13 12 11 10 9 8 TRGDLYCNT 7 6 5 4 3 2 1 0 TRGDLYDIV EXTFEN EXTREN CHSEL Bits Description 31 24 EXTSMPT ADC Sampling Time Extend When A D converting at high conversion...

Page 955: ...other Reserved NOTE Refer PWM_EADCTS0 PWM_EADCTS1 and TIMERn_CTL n 0 3 to get more information for PWM trigger and timer trigger 15 8 TRGDLYCNT A D Sample Module Start of Conversion Trigger Delay Tim...

Page 956: ...L Bits Description 3 0 CHSEL A D Sample Module Channel Selection 00H EADC_CH0 01H EADC_CH1 02H EADC_CH2 03H EADC_CH3 04H EADC_CH4 05H EADC_CH5 06H EADC_CH6 07H EADC_CH7 08H EADC_CH8 09H EADC_CH9 0AH E...

Page 957: ...SCTL12 EADC_BA 0xB0 R W A D Sample Module 12 Control Register 0x0000_0000 EADC_SCTL13 EADC_BA 0xB4 R W A D Sample Module 13 Control Register 0x0000_0000 EADC_SCTL14 EADC_BA 0xB8 R W A D Sample Module...

Page 958: ...TE Refer PWM_EADCTS0 PWM_EADCTS1 and TIMERn_CTL n 0 3 to get more information for PWM trigger and timer trigger 15 8 TRGDLYCNT A D Sample Module Start of Conversion Trigger Delay Time Trigger delay ti...

Page 959: ...L Bits Description 3 0 CHSEL A D Sample Module Channel Selection 00H EADC_CH0 01H EADC_CH1 02H EADC_CH2 03H EADC_CH3 04H EADC_CH4 05H EADC_CH5 06H EADC_CH6 07H EADC_CH7 08H EADC_CH8 09H EADC_CH9 0AH E...

Page 960: ...SCTL18 EADC_BA 0xC8 R W A D Sample Module 18 Control Register 0x0000_0000 31 30 29 28 27 26 25 24 EXTSMPT 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits...

Page 961: ...SPLIE7 SPLIE6 SPLIE5 SPLIE4 SPLIE3 SPLIE2 SPLIE1 SPLIE0 Bits Description 18 SPLIE18 Sample Module 18 Interrupt Enable Bit 0 Sample Module 18 interrupt Disabled 1 Sample Module 18 interrupt Enabled 17...

Page 962: ...Sample Module 7 interrupt Enabled 6 SPLIE6 Sample Module 6 Interrupt Enable Bit 0 Sample Module 6 interrupt Disabled 1 Sample Module 6 interrupt Enabled 5 SPLIE5 Sample Module 5 Interrupt Enable Bit...

Page 963: ...monitor the external analog input pin voltage transition without imposing a load on software 15 CMPWEN Compare Window Mode Enable Bit 0 ADCMPF0 EADC_STATUS2 4 will be set when EADC_CMP0 compared condi...

Page 964: ...EADC_DAT14 is selected to be compared 01111 Sample Module 15 conversion result EADC_DAT15 is selected to be compared 10000 Sample Module 16 conversion result EADC_DAT16 is selected to be compared 100...

Page 965: ...0 0x0000_0000 31 30 29 28 27 26 25 24 OV 15 8 23 22 21 20 19 18 17 16 OV 7 0 15 14 13 12 11 10 9 8 VALID 15 8 7 6 5 4 3 2 1 0 VALID 7 0 Bits Description 31 16 OV 15 0 EADC_DAT0 15 Overrun Flag It is a...

Page 966: ...4 Reserved 23 22 21 20 19 18 17 16 Reserved OV 18 16 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved VALID 18 16 Bits Description 31 19 Reserved Reserved 18 16 OV 18 16 EADC_DAT16 18 Overrun F...

Page 967: ...set to 1 Note This bit will keep 1 when any OVn Flag is equal to 1 26 AVALID for All Sample Module A D Result Data Register EADC_DAT Data Valid Flag Check n 0 18 0 None of sample module data register...

Page 968: ...sample module User can use it to monitor the external analog input pin voltage status 0 Conversion result in EADC_DAT less than CMPDAT3 setting 1 Conversion result in EADC_DAT great than or equal CMP...

Page 969: ...writing 1 to it 8 ADOVIF0 A D ADINT0 Interrupt Flag Overrun 0 ADINT0 interrupt flag is not overwritten to 1 1 ADINT0 interrupt flag is overwritten to 1 Note This bit is cleared by writing 1 to it 7 AD...

Page 970: ...D conversion of specific sample module has been completed 2 ADIF2 A D ADINT2 Interrupt Flag 0 No ADINT2 interrupt pulse received 1 ADINT2 interrupt pulse has been received Note1 This bit is cleared by...

Page 971: ...gister 3 0x0000_001F 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CURSPL Bits Description 31 5 Reserved Reserved 4 0 CURSPL...

Page 972: ...n 15 0 is not valid 1 Double data in RESULT EADC_DDATn 15 0 is valid This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EA...

Page 973: ...ence voltage INT_VREF VREF pin DAC maximum conversion updating rate 1M sps Supports voltage output buffer mode and bypass voltage output buffer mode Supports software and hardware trigger to start DAC...

Page 974: ...eds to be written into the specified register as follows 12 bit left alignment user has to load data into DAC_DAT 15 4 bits DAC_DAT 31 16 and DAC_DAT 3 0 are ignored in DAC conversion 12 bit right ali...

Page 975: ...5 Digital inputs are converted to output voltage on a linear conversion between 0 and reference voltage VREF The analog output voltage on DAC pin is determined by the following equation DAC_OUT VREF...

Page 976: ...error condition DMA data transfers are then disabled and no further DMA request is treated and DAC continues to convert last data An interrupt is also generated if the corresponding DMAURIEN DAC_CTL...

Page 977: ...ources in DAC controller one is DAC data conversion finish interrupt and the other is DMA under run interrupt When DAC conversion finish the FINISH DAC_STATUS 0 is set to 1 and an interrupt occurs whi...

Page 978: ...dress DAC_BA 0x4004_7000 DAC_CTL DAC_BA 0x00 R W DAC Control Register 0x0000_0000 DAC_SWTRG DAC_BA 0x04 R W DAC Software Trigger Control Register 0x0000_0000 DAC_DAT DAC_BA 0x08 R W DAC Data Holding R...

Page 979: ...on 31 14 Reserved Reserved 13 12 ETRGSEL External Pin Trigger Selection 00 Low level trigger 01 High level trigger 10 Falling edge trigger 11 Rising edge trigger 11 Reserved Reserved 10 LALIGN DAC Dat...

Page 980: ...DMAURIEN DMA Under run Interrupt Enable Bit 0 DMA underrun interrupt Disabled 1 DMA underrun interrupt Enabled 2 DMAEN DMA Mode Enable Bit 0 DMA mode Disabled 1 DMA mode Enabled 1 DACIEN DAC Interrupt...

Page 981: ...igger Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SWTRG Bits Description 31 1 Reserved Reserv...

Page 982: ...14 13 12 11 10 9 8 DAC_DAT 7 6 5 4 3 2 1 0 DAC_DAT Bits Description 31 16 Reserved Reserved 15 0 DAC_DAT DAC 12 bit Holding Data These bits are written by user software which specifies 12 bit conversi...

Page 983: ...0x0C R DAC Data Output Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved DATOUT 7 6 5 4 3 2 1 0 DATOUT Bits Description 31 12 Reser...

Page 984: ...on 31 9 Reserved Reserved 8 BUSY DAC Busy Flag Read Only 0 DAC is ready for next conversion 1 DAC is busy in conversion This is read only bit 7 2 Reserved Reserved 1 DMAUDR DMA Under Run Interrupt Fla...

Page 985: ...25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved SETTLET 7 6 5 4 3 2 1 0 SETTLET Bits Description 31 10 Reserved Reserved 9 0 SETTLET DAC Output Settling Time User softw...

Page 986: ...res Analog input voltage range 0 AVDD voltage of AVDD pin Supports hysteresis function Supports wake up function Selectable input sources of positive input and negative input ACMP0 supports 4 positive...

Page 987: ...TL1 2 NEGSEL ACMP_CTL1 5 4 INT_VREF CRVCTL ACMP_VREF 3 0 ACMP1_O ACMP01_INT ACMPOINV ACMP_CTL1 3 INTPOL ACMP_CTL1 9 8 0 1 Filter Block 0 1 OUTSEL ACMP_CTL1 12 FILTSEL ACMP_CTL1 15 13 ACMP0_O ACMPOINV...

Page 988: ...will be asserted and the corresponding flag ACMPIF0 ACMP_STATUS 0 and ACMPIF1 ACMP_STATUS 1 will be set to 1 The change condition of comparator output for interrupt flag can be selected by INTPOL ACM...

Page 989: ...oltage CRV 6 24 5 4 The comparator reference voltage CRV module is responsible for generating reference voltage for comparators The CRV module consists of resistor ladder and analog switch User can se...

Page 990: ...n Reset Value ACMP Base Address ACMP01_BA 0x4004_5000 ACMP_CTL0 ACMP01_BA 0x00 R W Analog Comparator 0 Control Register 0x0000_0000 ACMP_CTL1 ACMP01_BA 0x04 R W Analog Comparator 1 Control Register 0x...

Page 991: ...t Selection 000 Filter function is Disabled 001 ACMP0 output is sampled 1 consecutive PCLK 010 ACMP0 output is sampled 2 consecutive PCLKs 011 ACMP0 output is sampled 4 consecutive PCLKs 100 ACMP0 out...

Page 992: ...CMPOINV Comparator Output Inverse 0 Comparator 0 output inverse Disabled 1 Comparator 0 output inverse Enabled 2 HYSEN Comparator Hysteresis Enable Bit 0 Comparator 0 hysteresis Disabled 1 Comparator...

Page 993: ...ction is Disabled 001 ACMP1 output is sampled 1 consecutive PCLK 010 ACMP1 output is sampled 2 consecutive PCLKs 011 ACMP1 output is sampled 4 consecutive PCLKs 100 ACMP1 output is sampled 8 consecuti...

Page 994: ...Comparator Output Inverse Control 0 Comparator 1 output inverse Disabled 1 Comparator 1 output inverse Enabled 2 HYSEN Comparator Hysteresis Enable Bit 0 Comparator 1 hysteresis Disabled 1 Comparator...

Page 995: ...ke up interrupt event occurs 0 No power down wake up occurred 1 Power down wake up occurred Note Write 1 to clear this bit to 0 7 6 Reserved Reserved 5 ACMPO1 Comparator 1 Output Synchronized to the P...

Page 996: ...M451 May 4 2018 Page 996 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL Bits Description Note Write 1 to clear this bit to 0...

Page 997: ...00 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CRVSSEL Reserved CRVCTL Bits Description 31 7 Reserved Reserved 6 CRVSSEL C...

Page 998: ...4 7K DVCC VDDIO VBAT VDD VSS nRESET ICE_DAT ICE_CLK SWD Interface VREF 32 768kHz crystal 20p 20p X32_OUT X32_IN LDO CAP _ 1uF Reset Circuit VDD VSS SPI Device CS CLK MISO SPI_SS MOSI SPI_CLK SPI_MISO...

Page 999: ...4 2018 Page 999 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL 8 ELECTRICAL CHARACTERISTICS For information on the M451 series electrical characteristics please refer to NuMicro M451 Series D...

Page 1000: ...M451 May 4 2018 Page 1000 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL 9 PACKAGE DIMENSIONS LQFP 100L 14x14x1 4 mm footprint 2 0 mm 9 1...

Page 1001: ...M451 May 4 2018 Page 1001 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL LQFP 64L 10x10x1 4 mm footprint 2 0 mm 9 2...

Page 1002: ...M451 May 4 2018 Page 1002 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL LQFP 64L 7x7x1 4 mm footprint 2 0 mm 9 3...

Page 1003: ...M451 May 4 2018 Page 1003 of 1006 Rev 2 08 M451 SERIES TECHNICAL REFERENCE MANUAL LQFP 48L 7x7x1 4mm footprint 2 0mm 9 4...

Page 1004: ...6 17 7 2 Added bit field description for PWRDN ATTR 9 in section 6 17 7 3 Updated description field of register PDMA_TOCn in section 6 7 7 4 Revised bit length of RESULT EADC_DDATn in section 6 22 7...

Page 1005: ...CE MANUAL 2018 05 04 2 08 1 Revised the SWD interface in chapter 7 2 Added M452VE6AE and M452VG6AE in section 4 1 4 NuMicro M452 USB Series Selection Guide 3 Added section 4 2 8 NuMicro M452 USB Serie...

Page 1006: ...but is not limited to equipment for surgical implementation atomic energy control instruments airplane or spaceship instruments the control or operation of dynamic brake or safety systems designed for...

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