M451
May. 4, 2018
Page
661
of
1006
Rev.2.08
M4
51
S
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L RE
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NC
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01 = Reserved.
10 = Reserved.
11 = Inverse convention.
Note:
If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored.
[3]
AUTOCEN
Auto Convention Enable Bit
0 = Auto-convention Disabled.
1 = Auto-convention Enabled. When hardware receives TS in answer to reset state and
the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically,
otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11.
If software enables auto convention function, the setting step must be done before Answer
to Reset state and the first data must be 0x3B or 0x3F. After hardware received first data
and stored it at buffer, hardware will decided the convention and change the CONSEL
(SC_CTL[5:4]) bits automatically. If the first data is not 0x3B or 0x3F, hardware will
generate an interrupt INT_ACON_ERR (if ACERRIEN (SC_INTEN[10]) = 1 to CPU.
[2]
TXOFF
TX Transition Disable Control
0 = The transceiver Enabled.
1 = The transceiver Disabled.
[1]
RXOFF
RX Transition Disable Control
0 = The receiver Enabled.
1 = The receiver Disabled.
Note:
If AUTOCEN (SC_CTL[3])is enabled, these fields must be ignored.
[0]
SCEN
SC Engine Enable Bit
Set this bit to 1 to enable SC operation. If this bit is cleared, SC will force all transition to
IDLE state.
