M451
May. 4, 2018
Page
703
of
1006
Rev.2.08
M4
51
S
E
RI
E
S
T
E
CH
NICA
L RE
F
E
R
E
NC
E
M
A
NU
A
L
SMBDAT
SMBCLK
T
LOW:SEXT
T
LOW:MEXT
Clk
ACK
Clk
ACK
T
LOW:MEXT
T
LOW:MEXT
Start
Stop
Figure 6.15-19 SM Bus Time Out Timing
Bus management time-out:
1.
The SCLK low time-out condition when bus no IDLE
T
Time-out
= (BUSTO(I2C_BUSTOUT[7:0]) +1) x 16x1024 (14-bit) x T
PCLK
(if TOCDIV4 = 0).
= (BUSTO(I2C_BUSTOUT[7:0])+1) x 16x1024 (14-bit) x 4 x T
PCLK
(if TOCDIV4 = 1)
2.
The bus idle condition (both SCLK and SDA high) when bus IDLE
T
Time-out
= (BUSTO(I2C_BUSTOUT[7:0])+ 1) x 4 x T
PCLK
.
Bus clock low time-out:
In Master mode, the Master cumulative clock low extend time (T
LOW:MEXT
) is detected
In Slave mode, the slave cumulative clock low extend time (T
LOW:SEXT
) is detected
T
TLOW:EXT
= (CLKTO (I2C_CLKTOUT[7:0])+1) x 16x1024 (14-bit) x T
PCLK
(if TOCDIV4= 0).
= (CLKTO (I2C_CLKTOUT[7:0])+1) x 16x1024 (14-bit) x 4 x T
PCLK
(if TOCDIV4= 1)
Bus idle detection
A master can assume that the bus is free if it detects that the clock and data signals have been
high for T
IDLE
greater than T
HIGH,MAX
.
This timing parameter covers the condition where a master has been dynamically added to the
bus and may not have detected a state transition on the SMBCLK or SMBDAT lines. In this case,
the master must wait long enough to ensure that a transfer is not currently in progress. The
peripheral supports a hardware bus idle detection.
I
2
C Protocol Registers
6.15.5.3
To control I
2
C port through the following fifteen special function registers: I2C_CTL (control
register), I2C_STATUS (status register), I2C_DAT (data register), I2C_ADDRn (address registers,
n=0~3),I2C_ ADDRMSKn (address mask registers, n=0~3), I2C_CLKDIV (clock rate register),
I2C_TOCTL
(Time-out
control
register),
I2C_WKCTL(wake
up
control
register),
