M451
May. 4, 2018
Page
326
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1006
Rev.2.08
M4
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6.4.6 Register Description
ISP Control Register (FMC_ISPCTL)
Register
Offset
R/W
Description
Reset Value
FMC_ISPCTL
0x00
R/W
ISP Control Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
ISPFF
LDUEN
CFGUEN
APUEN
Reserved
BS
ISPEN
Bits
Description
[31:7]
Reserved
Reserved.
[6]
ISPFF
ISP Fail Flag (Write Protect)
This bit is set by hardware when a triggered ISP meets any of the following conditions:
This bit needs to be cleared by writing 1 to it.
(1) APROM writes to itself if APUEN is set to 0.
(2) LDROM writes to itself if LDUEN is set to 0.
(3) CONFIG is erased/programmed if CFGUEN is set to 0.
(4) Page Erase command at LOCK mode with ICE connection
(5) Erase or Program command at brown-out detected
(6) Destination address is illegal, such as over an available range.
(7) Invalid ISP commands
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[5]
LDUEN
LDROM Update Enable Bit (Write Protect)
LDROM update enable bit.
0 = LDROM cannot be updated.
1 = LDROM can be updated.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[4]
CFGUEN
CONFIG Update Enable Bit (Write Protect)
0 = CONFIG cannot be updated.
1 = CONFIG can be updated.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[3]
APUEN
APROM Update Enable Bit (Write Protect)
0 = APROM cannot be updated when the chip runs in APROM.
1 = APROM can be updated when the chip runs in APROM.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
