M451
May. 4, 2018
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Rev.2.08
M4
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In 2-Bit Transfer mode, the transmit data is loaded into shift register after 2 datum have been
written into the TX FIFO buffer. It uses 2 shift registers and 2 4-level skew buffers concurrently.
The detail timing of 2-Bit Transfer mode, please refer to the section of Two-Bit Transfer mode.
TXEMPTY = 1
Data 0
TXEMPTY = 0
Write
2 Data
TXEMPTY = 1
H/W load TX
Buffer into
Shift Register
b31|b30...b1|b0
TXEMPTY = 1
Data0
0 0 b31...b4|b3
Data0
b0
b1
b2
TX Buffer
TX Shift Register
TX Skew Buffer
H/W load Shift
Register into
Skew Buffer
Data 1
b31|b30...b1|b0
Data1
b0
b1
b2
0 0 b31...b4|b3
Data1
SPI0_MOSI0
SPI0_MOSI1
Example :
TWOBIT = 1
DWIDTH =0
LSB = 1
Figure 6.16-21 Two-Bit Transfer Mode FIFO Buffer Example
In Slave 3-Wire mode, the first 2-bit data is un-predicted (keep on the level of last bit in previously
transfer) if the data is written into TX FIFO among 3 peripheral clock cycles before the SPI bus
clock is presented. The other bits are held by TXUFPOL (SPI_FIFOCTL[6]) because there is TX
underflow event. The written data will be transmitted in the next transfer.
SPIn_CLK
SPIn_MISO
TXEMPTY
TXUFPOL
TXUFIF
Data 0 is written into TX FIFO Buffer among 3 peripheral
clock cycles before SPI bus clock is presented
Data 0
Unknown
1st transaction word
Less than 3 slave
peripheral clock cycles
Figure 6.16-22 TX Underflow Event (Slave 3-Wire Mode Enabled)
In Slave mode, during receiving operation, the serial data is received from SPIn_MOSI0/1 pin and
stored to SPI_RX register. The reception mechanism is similar to Master mode reception
operation. If the receive FIFO buffer contains 8 unread data, the RXFULL (SPI_STATUS[9]) will
be set to 1 and the RXOVIF (SPI_STATUS[11]) will be set 1 if there is more serial data is
received from SPIn_MOSI and follow-up data will be dropped (refer to the Receive FIFO Buffer
Example figure). If the receive bit count mismatch with the DWIDTH (SPI_CTL[12:8]) when the
slave selection line goes to inactive state, the SLVBEIF (SPI_STATUS[6]) will be set to 1.
