M451
May. 4, 2018
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Rev.2.08
M4
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counter to the register RCAPDATn (PWM_RCAPDATn[15:0]) or the register FCAPDATn
(PWM_FCAPDATn[15:0]) if the input channel has a rising transition or a falling transition,
respectively. The capture function will also generate an interrupt CAP_INT (using PWM_INT
vector) if the rising or falling latch occurs and the
corresponding channel n’s rising or falling
interrupt enable bits are set, where the CAPRIENn (PWM_CAPIEN[5:0]) is for the rising edge and
the CAPFIENn (PWM_CAPIEN[13:8]) is for the falling edge. When rising or falling latch occurs,
the corresponding PWM counter may be reloaded with the value PWM_PERIODn, depending on
the setting of RCRLDENn or FCRLDENn (where RCRLDENn and FCRLDENn are located at
PWM_CAPCTL[21:16] and PWM_CAPCTL[29:24], respectively). Note that the corresponding
GPIO pins must be configured as the capture function by enable the CAPINENn
(PWM_CAPINEN[5:0]) for the corresponding capture channel n. Figure 6.9-41 is the capture
block diagram of channel 0.
0
1
16-bits PWM
up/down counter
CNT
(PWM_CNT0[15:0])
DIRF
(PWM_CNT0[16])
PERIOD
(PWM_PERIOD0)
RCAPPAT
(PWM_RCAPDAT0[15:0])
FCAPDAT
(PWM_FCAPDAT0[15:0])
CAPEN0
(PWM_CAPCTL[0])
CAPINV0
(PWM_CAPCTL[8])
CAPINEN0
(PWM_CAPINEN[0])
PWM_CH0
RCRLDEN0
(PWM_CAPCTL[16])
FCRLDEN0
(PWM_CAPCTL[24])
Note:
denotes rising edge detect
denotes falling edge detect
Rising Latch
Falling Latch
Figure 6.9-41 PWM_CH0 Capture Block Diagram
Figure 6.9-42 illustrates the capture function timing. In this case, the capture counter is set as
PWM down counter type and the PERIOD is set to 8 so that the counter counts in the down
direction, from 8 to 0. When detecting a falling edge at the capture input pin, the capture function
latches the counter value to the PWM_FCAPDATn. When detecting the rising edge, it latches the
counter value to the PWM_RCAPDATn. In this timing diagram, when the falling edge is detected
at the first time, the capture function will reload the counter value from the PERIOD setting
because the FCRLDENn is enabled. But at the second time, the falling edge does not result in a
reload because of the disabled FCRLDENn. In this example, the counter also reloads at the rising
edge of the capture input because the RCRLDENn is enabled, too.
Moreover, if the case is setup as the up counter type, the counter will reload the value zero and
count up to the value PERIOD.
Figure 6.9-42 also illustrates the timing example for the interrupt and interrupt flag generation.
