M451
May. 4, 2018
Page
979
of
1006
Rev.2.08
M4
51
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6.23.7 Register Description
DAC Control Register (DAC_CTL)
Register
Offset
R/W
Description
Reset Value
DAC_CTL
0x00
R/W
DAC Control Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
ETRGSEL
Reserved
LALIGN
Reserved
BYPASS
7
6
5
4
3
2
1
0
TRGSEL
TRGEN
DMAURIEN
DMAEN
DACIEN
DACEN
Bits
Description
[31:14]
Reserved
Reserved.
[13:12]
ETRGSEL
External Pin Trigger Selection
00 = Low level trigger.
01 = High level trigger.
10 = Falling edge trigger.
11 = Rising edge trigger.
[11]
Reserved
Reserved.
[10]
LALIGN
DAC Data Left-aligned Enabled Control
0 = Right alignment.
1 = Left alignment.
[9]
Reserved
Reserved.
[8]
BYPASS
Bypass Buffer Mode
0 = Output voltage buffer Enabled.
1 = Output voltage buffer Disabled.
[7:5]
TRGSEL
Trigger Source Selection
000 = Software trigger.
001 = External pin STDAC trigger.
010 = Timer 0 trigger.
011 = Timer 1 trigger.
100 = Timer 2 trigger.
101 = Timer 3 trigger.
110 = PWM0 trigger.
111 = PWM1 trigger.
[4]
TRGEN
Trigger Mode Enable Bit
0 = DAC event trigger mode Disabled.
