M451
May. 4, 2018
Page
250
of
1006
Rev.2.08
M4
51
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IRQ0 ~ IRQ63 Interrupt Priority Register (NVIC_IPR1)
Register
Offset
R/W
Description
Reset Value
NVIC_IPR1
0x300 R/W
IRQ0 ~ IRQ63 Priority Control Register
0x0000_0000
31
30
29
28
27
26
25
24
PRI_4n_3
Reserved
23
22
21
20
19
18
17
16
PRI_4n_2
Reserved
15
14
13
12
11
10
9
8
PRI_4n_1
Reserved
7
6
5
4
3
2
1
0
PRI_4n_0
Reserved
Bits
Description
[31:28]
PRI_4n_3
Priority of 3
“0” denotes the highest priority and “15” denotes the lowest priority
[27:24]
Reserved
Reserved.
[23:20]
PRI_4n_2
Priority of 2
“0” denotes the highest priority and “15” denotes the lowest priority
[19:16]
Reserved
Reserved.
[15:12]
PRI_4n_1
Priority of 1
“0” denotes the highest priority and “15” denotes the lowest priority
[11:8]
Reserved
Reserved.
[7:4]
PRI_4n_0
Priority of 0
“0” denotes the highest priority and “15” denotes the lowest priority
[3:0]
Reserved
Reserved.
