M451
May. 4, 2018
Page
369
of
1006
Rev.2.08
M4
51
S
E
RI
E
S
T
E
CH
NICA
L RE
F
E
R
E
NC
E
M
A
NU
A
L
Port A-F Interrupt Type Control (Px_INTTYPE)
Register
Offset
R/W
Description
Reset Value
PA_INTTYPE
0x018
R/W
PA Interrupt Trigger Type Control
0x0000_0000
PB_INTTYPE
0x058
R/W
PB Interrupt Trigger Type Control
0x0000_0000
PC_INTTYPE
0x098
R/W
PC Interrupt Trigger Type Control
0x0000_0000
PD_INTTYPE
0x0D8
R/W
PD Interrupt Trigger Type Control
0x0000_0000
PE_INTTYPE
0x118
R/W
PE Interrupt Trigger Type Control
0x0000_0000
PF_INTTYPE
0x158
R/W
PF Interrupt Trigger Type Control
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
TYPE
7
6
5
4
3
2
1
0
TYPE
Bits
Description
[31:16]
Reserved
Reserved.
[n]
n=0,1..15
TYPE
Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or
by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by
de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK
clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers
RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set,
the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is
level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D.
Max. n=14 for port E.
Max. n=7 for port F.
Note2:
The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is
ignored for M45xD/M45xC.
