Nuvoton ARM Cortex NuMicro M451 Series, Technical Reference Manual

Page: 376 / 1006

M451
May. 4, 2018 Page 376 of 1006 Rev.2.08
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Interrupt De-bounce Control Register (GPIO_DBCTL)
Register Offset R/W Description Reset Value
GPIO_DBCTL 0x440 R/W Interrupt De-bounce Control Register 0x0000_0020
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved ICLKON DBCLKSRC DBCLKSEL
Bits Description
[31:6] Reserved Reserved.
[5] ICLKON
Interrupt Clock on Mode
0 = Edge detection circuit is active only if I/O pin corresponding RHIEN
(Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
1 = All I/O pins edge detection circuit is always active after reset.
Note: It is recommended to disable this bit to save system power if no special application
concern.
[4] DBCLKSRC
De-bounce Counter Clock Source Selection
0 = De-bounce counter clock source is the HCLK.
1 = De-bounce counter clock source is the 10 kHz internal low speed RC oscillator
(LIRC).
[3:0]
DBCLKSEL
De-bounce Sampling Cycle Selection
0000 = Sample interrupt input once per 1 clocks.
0001 = Sample interrupt input once per 2 clocks.
0010 = Sample interrupt input once per 4 clocks.
0011 = Sample interrupt input once per 8 clocks.
0100 = Sample interrupt input once per 16 clocks.
0101 = Sample interrupt input once per 32 clocks.
0110 = Sample interrupt input once per 64 clocks.
0111 = Sample interrupt input once per 128 clocks.
1000 = Sample interrupt input once per 256 clocks.
1001 = Sample interrupt input once per 2*256 clocks.
1010 = Sample interrupt input once per 4*256 clocks.
1011 = Sample interrupt input once per 8*256 clocks.
1100 = Sample interrupt input once per 16*256 clocks.
1101 = Sample interrupt input once per 32*256 clocks.
1110 = Sample interrupt input once per 64*256 clocks.
1111 = Sample interrupt input once per 128*256 clocks.