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M451
May. 4, 2018
Page
334
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1006
Rev.2.08
M4
51
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ISP Status Register (FMC_ISPSTS)
Register
Offset
R/W
Description
Reset Value
FMC_ISPSTS
0x40
R/W
ISP Status Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
VECMAP
15
14
13
12
11
10
9
8
VECMAP
Reserved
7
6
5
4
3
2
1
0
Reserved
ISPFF
PGFF
Reserved
CBS
ISPBUSY
Bits
Description
[31:24]
Reserved
Reserved.
[23:9]
VECMAP
Vector Page Mapping Address (Read Only)
All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address
{VECMAP[14:0], 9’h000} ~ {VECMAP[14:0], 9’h1FF}
[8:7]
Reserved
Reserved.
[6]
ISPFF
ISP Fail Flag (Write Protect)
This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to
FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP
meets any of the following conditions:
(1) APROM writes to itself if APUEN is set to 0.
(2) LDROM writes to itself if LDUEN is set to 0.
(3) CONFIG is erased/programmed if CFGUEN is set to 0.
(4) Page Erase command at LOCK mode with ICE connection
(5) Erase or Program command at brown-out detected
(6) Destination address is illegal, such as over an available range.
(7) Invalid ISP commands
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
[5]
PGFF
Flash Program with Fast Verification Flag (Read Only)
This bit is set if data is mismatched at ISP programming verification. This bit is clear by
performing ISP flash erase or ISP read CID operation
0 = Flash Program is success.
1 = Flash Program is fail. Program data is different with data in the flash memory
[4:3]
Reserved
Reserved.