FSB Design Guidelines
R
Intel
®
855PM Chipset Platform Design Guide
81
The ITP700FLEX debug port’s BCLKp/BCLKn inputs are driven with a 100-MHz differential clock
from the CK-408 clock chip. The CK-408 also feeds another two pairs of 100-MHz differential clocks
to the processor BCLK[1:0] and MCH BCLK[1:0] input pins. Common clock signal timing
requirements of the MCH and the processor requires matching of processor and MCH BCLK[1:0] nets
L6 and L7, respectively. To guarantee correct operation of ITP700FLEX, the BCLKp/BCLKn net L8
should be tuned to be within ± 50 ps to the sum of length L6 of the BCLK[1:0] lines and the additional
length L2 of the BPM#[4:0] signals.
i.e. L6 + L2 = L8 (within ± 50 ps)
The timing requirements for the BPM[5:0]#, RESET#, and BCLKp/BCLKn signals of the ITP700FLEX
debug port requires careful attention to their routing. Standard high frequency bus routing practices
should be observed.
1.
Keep a minimum of 2:1 spacing in between these signals and to other signals.
2.
Reference these signals to ground planes and avoid routing across power plane splits.
3.
The number of routing layer transitions should be minimized. If layout constraints require a
routing layer transition, any such transition should be accompanied with ground stitching vias
placed within 100mils of the signal via with at least one ground via for every two signals making
a layer transition.
DBR# should be routed to the system reset logic (e.g. the SYSRST# signal of the ICH4-M)
and initiate the equivalent of a front panel reset commonly found in desktop systems. The 150-
to 240-
pull-up resistor should be placed within 1 ns of the ITP700FLEX connector. Note
that the CPU should
not
be power cycled when DBR# is asserted.
DBA# is an optional system signal that can be used to indicate to the system that the ITP/TAP
port is being used. If not implemented, this signal can be left as no connect. If implemented, it
should be routed with a 150-
to 240-
pull-up resistor placed within 1ns of the
ITP700FLEX connector. See the
ITP700 Debug Port Design Guide
for more details on DBA#
usage.
The ITP700FLEX VTT and VTAP pins should be shorted together and connected to the V
CCP
(1.05 V) plane with a 0.1-µF decoupling capacitor placed within 0.1 inch of the VTT pins.
Table 17 summarizes termination resistors values, placement, and voltages the ITP signals need to
connect to for proper operation for onboard ITP700FLEX debug port.
