Platform Power Requirements
R
Intel
®
855PM Chipset Platform Design Guide
111
neither the primary nor the secondary side V
CC-CORE
floods make one continuous, robust connection
from “north to south.”
The remaining three, 10-µF, 0805 capacitors are placed on the primary side immediately above the
shadow of the three 0805 capacitors on the secondary side and are placed at the same pitch (90 mils) as
shown in Figure 60 and Figure 61. Two are on the side closest to the signal column 24 and 25 of the
processor pins while one is on the side closest to signal column 2. The area in between these three
capacitors can be efficiently used for VRM sense resistor connections as illustrated in the primary side
zoom in view in Figure 61.
Special care should be taken to provide a robust connection on the V
CC-CORE
floods on the primary side
from the sense resistors to the V
CC-CORE
corridor pins on the north side of the processor socket. This
robust connection is needed due to the presence of the GND dog bones on the primary side. The specific
arrangement of V
CC-CORE
and GND vias as shown in Figure 61 should be closely followed to provide a
robust connection to the V
CC-CORE
floods for
ALL
V
CC-CORE
BGA balls and vias on the primary side in
the AF, AE, AD, AC, AB, AA, Y, W, V, and U signal rows of the processor socket connecting all the
way up to V
CC-CORE
stitching vias next to negative terminals of the nine 0805 capacitors placed under the
socket cavity shadow.
Figure 63 shows a magnified view of the recommended layout for the SP capacitor connections to
minimize their inductance on the secondary side (Layer 8) of the motherboard. The V
CC-CORE
pin side of
the capacitor has two V
CC-CORE
vias placed 82 mils above the V
CC-CORE
pad of the SP capacitor within the
shadow of the SP capacitor. These two V
CC-CORE
vias are paired with two GND vias with a 50-mil offset
to reduce the inductance of the connection between the capacitor and the plane. An additional pair of
GND vias are placed 82 mils below the ground pad of the SP capacitor (also under the shadow of the SP
capacitor body) to allow efficient stitching of ground planes on Layers 1, 2, 4, 7, and 8 in this area.
Outside the shadow of the SP capacitors, the V
CC-CORE
/GND via pairs of the SP capacitors are shared
with the V
CC-CORE
/GND via pairs of the 0805 capacitors. The placement of additional vias is not advised
since this will result in excessive perforation of the internal power planes due to the antipad voids. The
pitch between the SP caps is 220 mils (or closer).
The layout concepts described in Figure 58 through Figure 63 result in an estimated V
CC-CORE
effective
resistance of 0.58 m
and an effective inductance of ~41 pH. Despite the use of multiple power planes,
this is still significant compared to the 3-m
load line target resistance and compared to the 17.1 pH
(600 pH / 35) inductance of the thirty-five 0805 decoupling capacitors. If alternative layout solutions
are used, they should be implemented with a level of robustness greater than or equal to that in the
example above. In terms of robustness, this refers to creating a low resistance and inductance connection
between the bulk and mid frequency capacitors and the processor pins.
