System Memory Design Guidelines (DDR-SDRAM)
R
140
Intel
®
855PM Chipset Platform Design Guide
The command signals should be routed using a 1:2 trace to space ratio for signals within the command
group. There should be a minimum of 20 mils spacing to non-DDR related signals and DDR clock pairs
SCK/SCK#[5:0]. Command signals should be routed on inner layers with minimized external traces.
Table 28. Command Topology 1 Routing Guidelines
Parameter
Routing Guidelines
Figure
Notes
Signal Group
Command – SMA[12:0], SBS[1:0],
SRAS#, SCAS#, SWE#
1
Motherboard Topology
Daisy Chain with Parallel Termination
Reference Plane
Ground Referenced
Characteristic Trace Impedance (Zo)
55
± 15%
Trace Width
Inner layers: 4 mils
Outer layers: 5 mils
Trace to Space ratio
1:2 (e.g. 4 mil trace to 8 mil space)
Group Spacing
Isolation spacing for non-DDR related
signals = 20 mils minimum
Trace Length L1 – MCH Command Signal Ball to
First SO-DIMM Pad
Min = 1.0 inch
Max = 4.0 inches
Figure 79
3, 5
Trace Length L2 – First SO-DIMM Pad to Series
Resistor Pad
Max = 1.1 inches
Figure 79
3
Trace Length L3 – Series Resistor Pad to
Second SO-DIMM Pad
Max = 0.2 inches
Figure 79
3
Trace Length L4 – Second SO-DIMM Pad to
Parallel Resistor Pad
Max = 0.8 inches
Figure 79
Series Termination Resistor (Rs)
10
± 5%
Parallel Termination Resistor (Rt)
56
± 5%
Maximum Recommended Motherboard Via
Count Per Signal
6
2,
4
Length Matching Requirements
Command Signals to SCK/SCK#[5:0]
See Section 6.1.3.1.2 for details
NOTES:
1.
Recommended resistor values and trace lengths may change in a later revision of the design guide.
2.
Power distribution vias from Rt to Vtt are not included in this count.
3.
The overall maximum and minimum length to the SO-DIMM must comply with clock length matching
requirements.
4.
It is possible to route using 4 vias if one via is shared that connects to the SO-DIMM1 pad and parallel
termination resistor.
5.
L1 trace length does not include MCH package length and should not be used when calculating L1 length.
