Platform Design Checklist
R
288
Intel
®
855PM Chipset Platform Design Guide
14.4.2.3.
Required Strapping when ITP Debug Port Disable
1, 2
ITP Interposer
Pin Name
System
Pull up/Pull down
Series Termination
Resistor (
Notes
9
TCK
Pull down to GND
27
Pull down needs to be placed within
2.0” of CPU socket.
TDI
Pull up to VCCP
150
Pull up needs to be placed within 2.0” of
CPU socket.
TDO
Leave the signal as NC (No Connect).
TMS
Pull up to VCCP
39
Pull up needs to be placed within 2.0” of
CPU socket.
TRST#
Pull down to GND
680
Pull down needs to be placed within
2.0” of CPU socket.
NOTES:
1.
See Section 14.4.2.1 if ITP700FLEX connector is implemented.
2.
See Section 14.4.2.3 if NO processor ITP debug port solution is implemented.
3.
Default tolerance for resistors is +/-5% unless otherwise specified.
14.4.3. Thermal
Sensor
Platform recommendations and design guidelines provided by your diode thermal sensor vendor should
be adhered to ensure proper operation of your thermal sensor.
14.4.4. Decoupling
Recommendations
Decoupling Recommendations
1
Signal Configuration
F
Qty
Notes
9
VCCA[3:0]
10
µF
10 nF
4
4
VCCA[3:0] should be tied to Vcc1_8.
One 1206 form factor 10 µF and one 0603
form factor 10 nF capacitor pair should be
used for each VCCA pin.
See Section 5.3.1 for details on guidelines
for placement and routing of the VCCA
decoupling capacitors
VCC[Vcc_core]
220 µF
10 µF
4
35
Polymer Covered Aluminium
(SP, AO
Cap)
0805 MLCC, >=X6R
See Section 5.9.3 for details on guidelines
for placement and routing of the
VCC[Vcc_core] decoupling capacitors.
VCCP
150
µF
0.1 µF
1
10
Polymer Covered Tantalum (POSCAP,
Neocap, KO Cap)
0603 MLCC, >= X7R.
Place all capacitors next to CPU.
Also see Section 14.6.4 for VCCP
decoupling requirement at the MCH.
See Section 5.9.4 for details on Intel
processor and MCH VCCP voltage plane
