FSB Design Guidelines
R
Intel
®
855PM Chipset Platform Design Guide
59
4.1.4.1.7.
Topology 3: CMOS Signals Driven by Intel 82801DBM ICH4-M to Processor and
FWH – INIT#
The signal INIT# should adhere to the following routing and layout recommendations. Table 14 lists the
recommended routing requirements for the INIT# signal of the ICH4-M. The routing guidelines allow
both signals to be routed as either micro-strip or strip-lines using 55
± 15% characteristic trace
impedance. Figure 23 shows the recommended implementation for providing voltage translation
between the ICH4-M’s INIT# voltage signaling level and any firmware hub (FWH) that utilizes a 3.3 V
interface voltage (shown as a supply V_IO_FWH). See Section 4.1.4.2 for more details on the voltage
translator circuit. For convenience, the entire topology and required transistors and resistors for the
voltage translator is shown in Figure 23.
Series resistor Rs is a component of the voltage translator logic circuit and serves as a driver isolation
resistor. Rs is shown separated by distance L3 from the first bipolar junction transistor (BJT), Q1, to
emphasize the placement of Rs with respect to Q1. The placement of Rs a distance of L3 before the Q1
BJT is a specific implementation of the generalized voltage translator circuit shown in Figure 24. The
routing recommendations of transmission line L3 in Figure 23 is listed in Table 14 and Rs should be
placed at the beginning of the T-split of the trace from the ICH4-M’s INIT# pin.
Figure 23. Routing Illustration for Topology 3
Intel
Pentium M
processor
Intel
ICH4-M
L2
L3
L1
Rs
3.3V
3904
3904
Intel
FWH
L4
3.3V
Q1
Q2
R1
R2
V_IO_FWH
Table 14. Layout Recommendations for Topology 3
L1 + L2
L3
L4
Rs
R1
R2
Transmission Line
Type
0.5” – 12.0”
0” – 3.0”
0.5” – 6.0”
330
± 5%
1.3 k
± 5%
330
± 5%
Micro-strip
0.5” – 12.0”
0” – 3.0”
0.5” – 6.0”
330
± 5%
1.3 k
± 5%
330
± 5%
Strip-line
For details on INIT# assertion/deassertion timings, see Section 9.7.5 for more details.
