FSB Design Guidelines
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Intel
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855PM Chipset Platform Design Guide
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4.1.6.
Processor and Intel 855PM MCH Host Clock Signals
Figure 28 illustrates processor and Intel 855PM MCH host clock signal routing. Both the processor and
the MCH’s BCLK[1:0] signals are initially routed from the CK-408 clock generator on Layer 3. Figure
13 shows how vertical routing on both Layer 3 and Layer 6 is blocked by the FSB address signals’
horizontal routing. Thus, a transition to secondary side layer routing is needed to complete the
BCLK[1:0] routing to the processor’s pins. In the recommended routing example (Figure 28) secondary
side layer routing of BCLK[1:0] is 507 mils long. To meet length-matching requirements between the
processor and MCH’s BCLK[1:0] signals, a similar transition from Layer 3 to the secondary side layer
is done next to the MCH package outline. Routing of the MCH’s BCLK[1:0] signals on the secondary
side is also trace tuned to 507 mils. BCLK[1:0] layer transition vias are accompanied by GND stitching
vias. For similar reasons, routing for the ITP interposer’s BCLK[1:0] signals also transition from Layer
3 to the secondary side layer and have 507-mil long traces on this layer. Throughout the routing length
on Layer 3, BCLK[1:0] signals should reference a solid GND plane on Layer 2 and Layer 4 as shown in
Figure 10. See Section 10.2.1 for more details on host clock topologies and routing recommendations.
If a system supports either the on-board ITP700FLEX connector or ITP Interposer only, then differential
host clock routing to either the ITP700FLEX connector or CPU socket but not both, is required.
